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MSM8128S-12

Description
Standard SRAM, 128KX8, 120ns, CMOS, CDIP32, 0.600 INCH, DIP-32
Categorystorage    storage   
File Size583KB,10 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

MSM8128S-12 Overview

Standard SRAM, 128KX8, 120ns, CMOS, CDIP32, 0.600 INCH, DIP-32

MSM8128S-12 Parametric

Parameter NameAttribute value
MakerAPTA Group Inc
Parts packaging codeDIP
package instruction0.600 INCH, DIP-32
Contacts32
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time120 ns
I/O typeCOMMON
JESD-30 codeR-CDIP-T32
length40.655 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum seat height4.3 mm
Maximum standby current0.002 A
Minimum standby current4.5 V
Maximum slew rate0.07 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width15.24 mm
128K x 8 SRAM
MSM8128 - 70/85/10/12
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 4.6: June 2002
Description
The MSM8128 is a 1Mbit monolithic SRAM
organised as 128K x 8. It is currently available
in DIL package with access times of 70, 85,
100, 120ns. It has a low power standby version
and has 3.0V battery backup capability. It is
directly TTL compatible and has common data
inputs and outputs.
Two pinout variants (single and dual CS) are
available.
All versions may be screened in accordance with
MIL-STD-883.
131,072 x 8 CMOS Static RAM
Features
Access Times of 70/85/100/120 ns
JEDEC standard Dual CS footprints.
Operating Power
550 mW (max)
Low Power Standby (-L) 2.2 mW (max)
Low Voltage Data Retention.
Completely Static Operation
Directly TTL compatible.
May be processed in accordance with MIL-STD-883
Block Diagram
Pin Definition
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8 TOP VIEW
S,V
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
D7
D6
D5
D4
D3
MEMORY ARRAY
512 X 2048
Package Details
Pin Count
Description
32
0.6" Dual-in-Line (DIP)
Package Type
S
Package details on pages 8 & 9.
See Page 9 for SX
Pin Functions
A0-A16
Address Inputs
D0-7
Data Input/Output
CS1
Chip Select 1
CS2
Chip Select 2
OE
Output Enable
WE
Write Enable
NC
No Connect
V
CC
Power (+5V)
GND
Ground
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