Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
FEATURES
•
Fastest 3V PLD
•
Supports 3/5V mixed systems
•
Low ground bounce (<1.1V worst case)
•
Live insertion/extraction permitted
•
Bus-hold data inputs eliminate the need for external pull-up
•
Metastable hardened device
•
High output drive capability: 32mA/–16mA
•
Varied product term distribution with up to 16 product terms per
•
Programmable output polarity
•
Available in 300 mil-wide 24-pin Plastic Small Outline Package
•
Design support provided for third party CAD development and
programming hardware
output for complex functions
resistors to hold unused inputs
PIN CONFIGURATIONS
D and N Packages
I0/CLK
I1
I2
I3
I4
I5
I6
I7
I8
1
2
3
4
5
6
7
8
9
24 V
CC
23 F9
22 F8
21 F7
20 F6
19 F5
18 F4
17 F3
16 F2
15 F1
14 F0
13 I11
I9 10
I10 11
GND 12
DESCRIPTION
The LVT22V10 is a versatile PAL® device fabricated on the Philips
BiCMOS QUBiC process.
The QUBiC process produces very high speed 3V devices (7.5ns)
which have excellent noise characteristics. Ground bounce of an
output held low while the remaining 9 outputs switch from high to
low is typically less than 0.7V. V
CC
bounce of an output held high
while the remaining 9 outputs switch from low to high is typically less
than 1.0V.
The LVT22V10 was designed to support mixed 3/5V systems. The
inputs are capable of handling 7V while the outputs can be pulled up
to 7V.
The designer can interface directly from 5V outputs (CMOS full rail
or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V
TTL input directly, or in the case of a CMOS input, the LVT output
can interface with the use of an external pull-up resistor. Finally, no
external pull-up resistors are needed on unused input pins due to a
bus-hold data structure designed into the LVT input.
The LVT22V10 has been designed with high drive outputs (32mA
sink and 16mA source currents), which allows for direct connection
to a backplane bus. This feature eliminates the need for additional,
standalone bus drivers, which are traditionally required to boost the
drive of a standard PLDs.
The LVT22V10 outputs are designed to support Live
Insertion/Extraction into powered up systems. The output is
specially designed so that during V
CC
ramp, the output remains
3-Stated until V
CC
[
2.1V. At that time the outputs become fully
functional depending upon device inputs. (See DC Electrical
Characteristics, Symbol I
PU/PD,
Page 5). In addition when an
LVT22V10 output is tied to a 5V bus, no bus current is loaded.
The LVT22V10 uses the familiar AND/OR logic array structure,
which allows direct implementation of sum-of-products equations.
This device has a programmable AND array which drives a fixed OR
array. The OR sum of products feeds an “Output Macro Cell” (OMC)
which can be individually configured as a dedicated input, a
combinatorial output, or a registered output with internal feedback.
N = Plastic Dual In-Line Package (300mil-wide)
D = Plastic Small Outline Large (300mil-wide) Package
A Package (standard)
I2
4
I3 5
I4 6
I5 7
NC 8
I6 9
GND 10
I8 11
12
I9
13
14
15
16
17
18
I1
3
CLK/
I0 NC V
CC
F9 F8
2
1
28
27
26
25 F7
24 F6
23 F5
22 NC
21 F4
20 F3
19 F2
I10 GND NC I11 F0 F1
A = Plastic Leaded Chip Carrier
A Package (evolutionary)
I2
4
I3 5
I4 6
I5 7
GND 8
I6 9
I7 10
I8 11
12
I9
13
14
15
16
17
18
I1
3
CLK/
I0 V
CC
V
CC
F9 F8
2
1
28
27
26
25 F7
24 F6
23 F5
22 GND
21 F4
20 F3
19 F2
I10 GND GND I11 F0 F1
A = Plastic Leaded Chip Carrier
SP00436
®PAL
is a registered trademark of Advanced Micro Devices, Inc.
1998 Feb 10
2
853-1759 18947
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP (300mil)
28-Pin PLCC (standard pinout)
28-Pin PLCC (evolutionary pinout)
24-Pin Plastic SOL
ORDER CODE
LVT22V10-7N
(8.0ns device)
DWG NUMBER
SOT222-1
SOT261-3
SOT261-3
SOT137-1
LVT22V10B7A (7.5ns device)
LVT22V10-7A
LVT22V10-7D
(7.5ns device)
(8.0ns device)
PIN LABEL DESCRIPTIONS
SYMBOL
I1 – I11
F0 – F9
CLK/I0
V
CC
GND
NC
DESCRIPTION
Dedicated Input
Macro Cell Input/Output
Clock Input/Dedicated Input
Supply Voltage
Ground
No Connection
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction
150°C
75°C
75°C
OPERATING RANGES
RATINGS
SYMBOL
V
CC
T
amb
PARAMETER
MIN
Supply voltage
Operating free-air
temperature
+3.0
0
MAX
+3.6
+75
V
DC
°C
UNIT
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
stg
Supply voltage
2
Input voltage
2
Output
voltage
3
Input currents
Output currents
Storage temperature range
–65
PARAMETER
RATINGS
MIN
–0.5
–0.5
–0.5
–30
MAX
+4.6
7
5.5
+30
+100
+150
UNIT
V
DC
V
DC
V
DC
mA
mA
°C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
2. Except in programming mode.
3. Outputs can be pulled up to 7V via external pull-up resistor.
1998 Feb 10
3
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
DC ELECTRICAL CHARACTERISTICS
Over operating ranges.
SYMBOL
Input voltage
V
IL
V
IH
V
I
Low
High
Clamp
V
CC
= MIN
V
CC
= MAX
V
CC
= MIN, I
IN
= –18mA
V
CC
= MIN to MAX, V
I
= V
IH
or V
IL
V
OH
High-level output voltage
V
CC
= MIN V
I
= V
IH
or V
IL
MIN,
V
CC
= MIN to MAX, V
I
= V
IH
or V
IL
V
OL
Low-level output voltage
V
CC
= MIN V
I
= V
IH
or V
IL
MIN,
I
OH
= –100
µA
I
OH
= –16mA
I
OH
= –5.5 mA
I
OL
= 100µA
I
OL
= 32 mA
I
OL
= 16 mA
V
CC
–0.2
2.0
2.4
0.2
0.5
0.4
–10
10
10
20
75
–75
500
–500
±10
±100
100
2.0
–1.2
0.8
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
PARAMETER
TEST CONDITIONS
1
LIMITS
MIN
MAX
UNIT
Output voltage
Input current
I
IL
I
IH
I
I
I
I
I
BHL
I
BHH
I
BHLO
I
BHHO
I
OFF
I
EX
I
PU/PD
Low
High
Max input current
Pin 1 (program)
Bus hold low sustaining current
2
Bus hold high sustaining
current
3
Bus hold low overdrive current
4, 9
Bus hold high overdrive current
5, 9
Output off current
Current into an output in high state
when V
O
> V
CC
Power-up/down 3-State output
current
8
Output leakage
6
Output
leakage
6
Short circuit
7
V
CC
supply current
V
CC
= MAX, V
IN
= 0.0V
V
CC
= MAX, V
IN
= V
CC
V
CC
= MAX, V
IN
= 5.5V
V
CC
= MAX, V
IN
= 5.5V
V
CC
= 3V, V
I
= 0.8V
V
CC
= 3V, V
I
= 2V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 0V, V
I
or V
O
= 0 to 4.5V
V
O
= 5.5V, V
CC
= 3.0V
V
CC
<1.2V; V
O
= 0.5V to V
CC
;
V
I
= GND or V
CC
; OE/OE = X
V
CC
= MAX
I
OZH
I
OZL
I
SC
I
CC
V
IN
= V
IL
or V
IH
, V
OUT
= 5.5V
V
IN
= V
IL
or V
IH
, V
OUT
=0V
V
OUT
= 0.5V
V
CC
= 3.6V, Outputs enabled, V
I
= V
CC
or GND; I
O
= 0
MIN
V
CC
= 3.0V, 25°C,
C
L
= 50pF (including jig capacitance)
V
CC
= 3.3V, 25°C, C
L
= 50pF
,
,
(including jig capacitance)
LVT22V10-7
LVT22V10B7
2.2
–30
10
–10
–220
170
TYP
2.3
0.7
1.0
1.1
1.1
MAX
µA
µA
mA
mA
UNIT
V
V
V
Output current
Ground/V
CC
Bounce
V
OHV
V
OLP
Maximum dynamic V
OH
Maximum dynamic V
OL
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. The bus hold circuit can sink at least the minimum low sustaining current at V
IL
MAX. I
BHL
should be measured after lowering V
IN
to GND
and then raising it to V
IL
MAX.
3. The bus hold circuit can source at least the minimum high sustaining current at V
IH
MIN. I
BHL
should be measured after raising V
IN
to V
CC
and then lowering it to V
IH MIN.
4. An external driver must source at least I
BHLO
to switch this node from low to high.
5. An external driver must sink at least I
BHHO
to switch this node from high to low.
6. I/O pin leakage is the worst case of I
OZX
or I
IX
(where X = H or L).
7. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. V
OUT
= 0.5V has been
chosen to avoid test problems caused by tester ground degradation.
8. This parameter is valid for any V
CC
between 0V and 1.2 V with a transition time up to 10 mS. From V
CC
= 1.2 to V
CC
= 3.3V
±0.3V
a
transition time of 100
µS
is permitted. X = Don’t care.
9. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where input
current may be affected.
1998 Feb 10
5
FPGA/CPLD
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