LFE2-70SE-7F900I datasheet, PDF

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LFE2-70SE-7F900I: DescriptionField Programmable Gate Array, PBGA900, 31 X 31 MM, FPBGA-900; CategoryProgrammable logic devices Programmable logic; File Size10MB，606 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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LFE2-70SE-7F900I Overview

Field Programmable Gate Array, PBGA900, 31 X 31 MM, FPBGA-900

LFE2-70SE-7F900I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	BGA
package instruction	BGA,
Contacts	900
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PBGA-B900
JESD-609 code	e0
length	31 mm
Humidity sensitivity level	3
Number of terminals	900
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.6 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	31 mm

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LatticeECP2/M Family Handbook

HB1003 Version 02.7, March 2007

LatticeECP2/M Family Handbook

Table of Contents

March 2007

Section I. LatticeECP2/M Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU Blocks ........................................................................................................................................................ 2-3

Slice .......................................................................................................................................................... 2-3

Modes of Operation................................................................................................................................... 2-5

Routing............................................................................................................................................................... 2-6

sysCLOCK Phase Locked Loops (GPLL/SPLL) ................................................................................................ 2-6

General Purpose PLL (GPLL) ................................................................................................................... 2-6

Standard PLL (SPLL) ................................................................................................................................ 2-7

Delay Locked Loops (DLL)................................................................................................................................. 2-8

DLLDELA Delay Block .............................................................................................................................. 2-9

PLL/DLL Cascading .................................................................................................................................. 2-9

GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only) .................................................. 2-10

Clock Dividers .................................................................................................................................................. 2-10

Clock Distribution Network ............................................................................................................................... 2-11

Primary Clock Sources............................................................................................................................ 2-11

Secondary Clock/Control Sources .......................................................................................................... 2-13

Edge Clock Sources................................................................................................................................ 2-14

Primary Clock Routing ............................................................................................................................ 2-15

Dynamic Clock Select (DCS) .................................................................................................................. 2-15

Secondary Clock/Control Routing ........................................................................................................... 2-15

Slice Clock Selection............................................................................................................................... 2-17

Edge Clock Routing ................................................................................................................................ 2-17

sysMEM Memory ............................................................................................................................................. 2-18

sysMEM Memory Block........................................................................................................................... 2-18

Bus Size Matching .................................................................................................................................. 2-19

RAM Initialization and ROM Operation ................................................................................................... 2-19

Memory Cascading ................................................................................................................................. 2-19

Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-19

Memory Core Reset ................................................................................................................................ 2-19

EBR Asynchronous Reset....................................................................................................................... 2-20

sysDSP™ Block ............................................................................................................................................... 2-20

sysDSP Block Approach Compare to General DSP ............................................................................... 2-21

sysDSP Block Capabilities ...................................................................................................................... 2-21

MULT sysDSP Element .......................................................................................................................... 2-22

MAC sysDSP Element ............................................................................................................................ 2-23

MULTADDSUB sysDSP Element ........................................................................................................... 2-24

MULTADDSUBSUM sysDSP Element ................................................................................................... 2-25

Clock, Clock Enable and Reset Resources ............................................................................................ 2-25

Signed and Unsigned with Different Widths............................................................................................ 2-26

OVERFLOW Flag from MAC .................................................................................................................. 2-26

IPexpress™............................................................................................................................................. 2-27

Optimized DSP Functions ................................................................................................................................ 2-27

Resources Available in the LatticeECP2/M Family ................................................................................. 2-27

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2/M DSP Performance .......................................................................................................... 2-28

Programmable I/O Cells (PIC) ......................................................................................................................... 2-28

PIO ................................................................................................................................................................... 2-30

Input Register Block ................................................................................................................................ 2-30

Output Register Block ............................................................................................................................. 2-32

Tristate Register Block ............................................................................................................................ 2-34

Control Logic Block ................................................................................................................................. 2-34

DDR Memory Support...................................................................................................................................... 2-34

Left and Right Edges............................................................................................................................... 2-34

Bottom Edge ........................................................................................................................................... 2-34

Top Edge................................................................................................................................................. 2-35

DLL Calibrated DQS Delay Block ........................................................................................................... 2-36

Polarity Control Logic .............................................................................................................................. 2-38

DQSXFER............................................................................................................................................... 2-39

sysIO Buffer ..................................................................................................................................................... 2-39

sysIO Buffer Banks ................................................................................................................................. 2-39

Typical sysIO I/O Behavior During Power-up.......................................................................................... 2-42

Supported sysIO Standards .................................................................................................................... 2-42

Hot Socketing.......................................................................................................................................... 2-44

SERDES and PCS (Physical Coding Sublayer)............................................................................................... 2-45

SERDES Block........................................................................................................................................ 2-45

PCS......................................................................................................................................................... 2-46

SCI (SERDES Client Interface) Bus........................................................................................................ 2-46

IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-47

Device Configuration........................................................................................................................................ 2-47

Software Error Detect (SED) Support ..................................................................................................... 2-48

External Resistor..................................................................................................................................... 2-48

On-Chip Oscillator................................................................................................................................... 2-48

Density Shifting ................................................................................................................................................ 2-49

DC and Switching Characteristics

Absolute Maximum Ratings ............................................................................................................................... 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

Hot Socketing Specifications.............................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-3

LatticeECP2 Supply Current (Standby).............................................................................................................. 3-4

LatticeECP2M Supply Current (Standby)........................................................................................................... 3-4

LatticeECP2 Initialization Supply Current .......................................................................................................... 3-5

LatticeECP2M Initialization Supply Current ....................................................................................................... 3-6

SERDES Power Supply Requirements (LatticeECP2M Family Only) ............................................................... 3-7

SERDES Power (LatticeECP2M Family Only)................................................................................................... 3-7

sysIO Recommended Operating Conditions...................................................................................................... 3-8

sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-9

sysIO Differential Electrical Characteristics ..................................................................................................... 3-10

LVDS....................................................................................................................................................... 3-10

Differential HSTL and SSTL.................................................................................................................... 3-10

LVDS25E ................................................................................................................................................ 3-11

BLVDS .................................................................................................................................................... 3-12

LVPECL .................................................................................................................................................. 3-13

RSDS ...................................................................................................................................................... 3-14

MLVDS.................................................................................................................................................... 3-15

Typical Building Block Function Performance.................................................................................................. 3-16

Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-16

Register-to-Register Performance .......................................................................................................... 3-16

Derating Timing Tables .................................................................................................................................... 3-17

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2/M External Switching Characteristics.......................................................................................... 3-18

LatticeECP2/M Internal Switching Characteristics ........................................................................................... 3-23

Timing Diagrams .............................................................................................................................................. 3-25

LatticeECP2/M Family Timing Adders ............................................................................................................. 3-27

sysCLOCK GPLL Timing ................................................................................................................................. 3-30

sysCLOCK SPLL Timing.................................................................................................................................. 3-31

DLL Timing....................................................................................................................................................... 3-32

SERDES High Speed Data Transmitter

(LatticeECP2M Family Only) ........................................................... 3-33

SERDES High Speed Data Receiver (LatticeECP2M Family Only) ................................................................ 3-34

Input Data Jitter Tolerance...................................................................................................................... 3-34

Input Eye Mask Characterization ............................................................................................................ 3-35

SERDES External Reference Clock (LatticeECP2M Family Only) ......................................................... 3-36

Power-Down/Power-Up Specification .............................................................................................................. 3-36

LatticeECP2/M sysCONFIG Port Timing Specifications .................................................................................. 3-37

JTAG Port Timing Specifications ..................................................................................................................... 3-42

Switching Test Conditions................................................................................................................................ 3-43

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-4

LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 .......................................................................... 4-5

LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 ........................................................................ 4-7

LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 ........................................................................ 4-9

LatticeECP2M Pin Information Summary......................................................................................................... 4-11

Available Device Resources by Package, LatticeECP2................................................................................... 4-13

LatticeECP2 Power Supply and NC................................................................................................................. 4-14

LatticeECP2 Power Supply and NC (Cont.)..................................................................................................... 4-15

LFE2-6E and LFE2-12E Logic Signal Connections: 144 TQFP....................................................................... 4-17

LFE2-12E and LFE2-20E Logic Signal Connections: 208 PQFP .................................................................... 4-21

LFE2-6E and LFE2-12E Logic Signal Connections: 256 fpBGA...................................................................... 4-26

LFE2-20 Logic Signal Connections: 256 fpBGA .............................................................................................. 4-34

LFE2-12E and LFE2-20E Logic Signal Connections: 484 fpBGA.................................................................... 4-49

LFE2-35E and LFE2-50E Logic Signal Connections: 484 fpBGA.................................................................... 4-61

LFE2-20 and LFE2-35 Logic Signal Connections: 672 fpBGA ........................................................................ 4-73

LFE2-50E and LFE2-70E Logic Signal Connections: 672 fpBGA.................................................................... 4-92

LFE2-70E Logic Signal Connections: 900 fpBGA.......................................................................................... 4-111

LFE2M35E Logic Signal Connections: 256 fpBGA ........................................................................................ 4-134

LFE2M35E Logic Signal Connections: 484fpBGA ......................................................................................... 4-142

LFE2M35E Logic Signal Connections: 672 fpBGA ........................................................................................ 4-155

Ordering Information

LatticeECP2 Part Number Description............................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

LatticeECP2 Devices, Conventional Packaging........................................................................................ 5-2

LatticeECP2 Devices, Lead-Free Packaging ..................................................................................................... 5-5

LatticeECP2M Part Number Description............................................................................................................ 5-8

Ordering Information .......................................................................................................................................... 5-8

LatticeECP2M Devices, Conventional Packaging..................................................................................... 5-9

LatticeECP2M Devices, Lead-Free Packaging ....................................................................................... 5-11

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

Revision History

Section II. LatticeECP2/M Family Technical Notes

LatticeECP2M SERDES/PCS Usage Guide

Features ............................................................................................................................................................. 8-1

Introduction to PCS ............................................................................................................................................ 8-1

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

Architecture Overview ........................................................................................................................................ 8-2

PCS Quad ................................................................................................................................................. 8-2

PCS Channel ............................................................................................................................................ 8-3

Per Channel PCS/FPGA Interface Ports................................................................................................... 8-4

SCI (SERDES Client Interface) Bus.......................................................................................................... 8-6

Using This Technical Note ........................................................................................................................ 8-6

SERDES ............................................................................................................................................................ 8-7

I/O Definitions............................................................................................................................................ 8-8

Reference Clock Usage .......................................................................................................................... 8-10

Configuration GUIs.................................................................................................................................. 8-11

Configuration File Description ................................................................................................................. 8-21

PCS.................................................................................................................................................................. 8-23

LatticeECP2M PCS Quad Module .......................................................................................................... 8-23

PCS Functional Setup...................................................................................................................................... 8-24

Auto-Configuration File ........................................................................................................................... 8-24

LatticeECP2M PCS 8-bit Modes ...................................................................................................................... 8-24

8-bit Mode Pin Description ............................................................................................................................... 8-26

Optional Pin Description................................................................................................................................... 8-30

8-bit Mode Detailed Description ....................................................................................................................... 8-31

Clocks & Resets...................................................................................................................................... 8-31

Transmit Data.......................................................................................................................................... 8-31

Receive Data........................................................................................................................................... 8-33

LatticeECP2M PCS in PCI Express Mode ....................................................................................................... 8-47

PCI Express Mode Pin Description .................................................................................................................. 8-48

PCI Express Mode Detailed Description .......................................................................................................... 8-50

LatticeECP2M PCS in PIPE Mode................................................................................................................... 8-52

PIPE Mode Pin Description..................................................................................................................... 8-54

LatticeECP2M PCS 10-bit Modes .................................................................................................................... 8-57

10-bit Mode Pin Description ............................................................................................................................. 8-58

PCS Loopback Testing .................................................................................................................................... 8-58

Serial Far-end Loopback Mode............................................................................................................... 8-58

PCS Parallel Far-end Loopback Mode.................................................................................................... 8-59

PCS Parallel Far-end Loopback Mode.................................................................................................... 8-60

SERDES Client Interface (SCI)........................................................................................................................ 8-61

Interrupts and Status............................................................................................................................... 8-63

Dynamic Configuration of SERDES/PCS Quad...................................................................................... 8-64

SERDES Debug Capabilities .................................................................................................................. 8-64

Memory Map .................................................................................................................................................... 8-65

Configuration Register Definition ............................................................................................................ 8-65

Per Quad Register Overview .................................................................................................................. 8-66

Per Quad PCS Control Register Details ................................................................................................. 8-67

Per Quad SERDES Control Register Details .......................................................................................... 8-70

Per Quad Reset and Clock Control Register Details .............................................................................. 8-72

Per Quad PCS Status Register Details................................................................................................... 8-73

Per Quad SERDES Status Register Details ........................................................................................... 8-75

Per Channel Register Overview.............................................................................................................. 8-76

Per Channel SERDES Control Register Details ..................................................................................... 8-79

Per Channel PCS Status Register Details .............................................................................................. 8-81

Per Channel SERDES Status Register Details....................................................................................... 8-82

Technical Support Assistance.......................................................................................................................... 8-84

Revision History ............................................................................................................................................... 8-84

Appendix A. 8b/10b Symbol Codes ................................................................................................................. 8-85

Appendix B. Attribute Cross-Reference Table ................................................................................................. 8-86

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