Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
FEATURES
•
Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
Two options are available, 74ABT16823A which does not have the
bus-hold feature and 74ABTH16823A which incorporates the
bus-hold feature.
•
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
•
Live insertion/extraction permitted
•
Power-up 3-State
•
74ABTH16823A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
•
Power-up Reset
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
PARAMETER
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent su ly current
supply
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
O
= 0V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5V
Outputs low; V
CC
= 5.5V
TYPICAL
2.3
1.9
4
6
500
9
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16823A DL
74ABT16823A DGG
74ABTH16823A DL
74ABTH16823A DGG
NORTH AMERICA
BT16823A DL
BT16823A DGG
BH16823A DL
BH16823A DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
2, 27
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
56, 29
55, 30
1, 28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
1998 Feb 27
SYMBOL
1OE, 2OE
1D0-1D8
2D0-2D8
1Q0-1Q8
2Q0-2Q8
1CP, 2CP
1CE, 2CE
1MR, 2MR
GND
V
CC
2
FUNCTION
Output enable input (active-Low)
Data inputs
Data outputs
Clock pulse input (active rising edge)
Clock enable input (active-Low)
Master reset input (active-Low)
Ground (0V)
Positive supply voltage
853-1791 19025
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
output in High state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
PARAMETER
MIN
4.5
0
2.0
0.8
–32
64
10
+85
MAX
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1998 Feb 27
5
FPGA/CPLD
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