Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A
74ABTH16841A
FEATURES
•
High speed parallel latches
•
Live insertion/extraction permitted
•
Extra data width for wide address/data paths or buses carrying
•
Power-up 3-State
•
74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
parity
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.
•
Power-up reset
•
Ideal where high speed, light loading, or increased fan-in are
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
required with MOS microprocessors
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
PARAMETER
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Quiescent supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
O
= 0V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5V
Outputs LOW; V
CC
= 5.5V
TYPICAL
3.1
2.2
4
7
500
10
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16841A DL
74ABT16841A DGG
74ABTH16841A DL
74ABTH16841A DGG
NORTH AMERICA
BT16841A DL
BT16841A DGG
BH16841A DL
BH16841A DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1D0 – 1D9
2D0 – 2D9
1Q0 – 1Q9
2Q0 – 2Q9
1OE, 2OE
1LE, 2LE
GND
V
CC
Data inputs
Data outputs
Output enable inputs (active-Low)
Latch enable inputs (active rising edge)
Ground (0V)
Positive supply voltage
FUNCTION
1998 Feb 27
2
853-1797 19025
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A
74ABTH16841A
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00024
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
PARAMETER
Min
4.5
0
2.0
0.8
–32
64
5
+85
Max
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1998 Feb 27
4
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A
74ABTH16841A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
Min
V
IK
V
OH
V
OL
V
RST
I
I
Input clamp voltage
High-level output voltage
Low-level output voltage
Power-up output
voltage
3
Input leakage current
In ut
74ABT16841A
Input leakage current
74ABTH16841A
Bus Hold current inputs
6
74ABTH16841A
Power-off leakage current
Power-up/down 3-State
output current
4
3-State output High current
3-State output Low current
Output High leakage current
Output current
1
Quiescent supply current
Additional supply current per
input pin
2
V
CC
= 4.5V; I
IK
= -18mA
V
CC
= 4.5V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 5.0V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= -32mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= V
CC
or GND
V
CC
= 5.5V; V
I
= V
CC
or GND
V
CC
= 5.5V; V
I
= V
CC
V
CC
= 5.5V; V
I
= 0
V
CC
= 4.5V; V
I
= 0.8V
V
CC
= 4.5V; V
I
= 2.0V
V
CC
= 5.5V; V
I
= 0 to 5.5V
I
OFF
I
PU/PD
I
OZH
I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don’t care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State; V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V, other inputs at
V
CC
or GND
–50
I
HOLD
Control pins
Data pins
5
ins
35
–75
±800
±5.0
±5.0
5.0
–5.0
5.0
–70
0.5
10
0.5
0.2
±100
±50
10
–10
50
–180
1
19
1
1
–50
±100
±50
10
–10
50
–180
1
19
1
1
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
2.5
3.0
2.0
Typ
–0.9
2.9
3.4
2.4
0.42
0.13
±0.01
±0.01
0.01
–2
0.55
0.55
±1
±1
1
–3
35
–75
µA
Max
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±1
1
–5
T
amb
= -40°C
to +85°C
Min
Max
–1.2
V
V
V
V
V
V
µ
µA
µA
µA
µA
UNIT
I
I
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10% a
transition time of up to 100µsec is permitted.
5. Unused pins at V
CC
or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
MIN
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
nDx to nQx
Propagation delay
nLE to nQx
Output enable time
to High and Low level
Output disable time
from High and Low level
2
1
4
5
4
5
1.1
1.5
1.5
1.0
1.2
1.2
1.8
1.5
T
amb
= +25
o
C
V
CC
= +5.0V
TYP
3.1
2.2
2.5
2.1
2.4
2.2
3.0
2.5
MAX
4.1
3.1
3.3
2.8
3.2
2.9
4.0
3.2
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±0.5V
MIN
1.1
1.5
1.5
1.0
1.2
1.2
1.8
1.5
MAX
4.9
3.6
3.7
3.1
4.0
3.6
4.9
3.7
ns
ns
ns
ns
UNIT
1998 Feb 27
5
Embedded System
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