HY62SF8100 Series
128Kx8bit full CMOS SRAM
DESCRIPTION
The HY62SF8100 is a high speed, low power and
1M bit full CMOS SRAM organized as 131,072
words by 8bit. The HY62SF8100 uses high
performance full CMOS process technology and
designed for high speed low power circuit
technology. It is particularly well suited for used in
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 1.5V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(LL/SL-part)
-. 1.5V(min) data retention
•
Standard pin configuration
-. 32 - sTSOPI - 8X13.4(Standard)
Product
Voltage
Speed
No.
(V)
(ns)
HY62SF8100
1.7~2.3
120/150/200
HY62SF8100-I
1.7~2.3
120/150/200
Note 1. Blank : Commercial, I : Industrial
2. Current value is max.
Operation
Current/Icc(mA)
5
5
Standby Current(uA)
LL
SL
5
1
5
1
Temperature
(°C)
0~70
-40~85(I)
PIN CONNECTION
( Top View )
A0
BLOCK DIAGRAM
ROW
DECODER
SENSE AMP
I/O1
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
ADD INPUT
BUFFER
BUFFER
COLUMN
DECODER
MEMORY ARRAY
128K x 8
WRITE DRIVER
A16
I/O8
/CS1
CONTROL
LOGIC
CS2
sTSOP I( Stanard )
/OE
/WE
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Pin Name
A0 ~ A16
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Address Input
Data Input/Output
Power( 1.7V~2.3V )
Ground
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.08 /Jun. 00
Hyundai Semiconductor
HY62SF8100 Series
ORDERING INFORMATION
Part No.
HY62SF8100LLST
HY62SF8100SLST
HY62SF8100LLST-I
HY62SF8100SLST-I
Speed
120/150/200
120/150/200
120/150/200
120/150/200
Power
LL-part
SL-part
LL-part
SL-part
Temp.
Package
sTSOP l (Standard)
sTSOP l (Standard)
sTSOP l (Standard)
sTSOP l (Standard)
I
I
Note 1. Blank : Commercial, I : Industrial
ABSOLUTE MAXIMUM RATING (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
T
STG
P
D
T
SOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.2 to 3.6
-0.2 to 4.6
0 to 70
-40 to 85
-55 to 150
1.0
260
•
10
Unit
V
V
°C
°C
°C
W
°C •
sec
Remark
HY62SF8100
HY62SF8100-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
Mode
Deselected
Deselected
Output Disabled
Read
Write
I/O
High-Z
High-Z
High-Z
Data Out
Data In
Power
Standby
Standby
Active
Active
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care(V
IH
or V
IL)
Rev.08 /Jun. 00
2
HY62SF8100 Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
1.7
0
1.6
-0.3
(1)
Typ.
1.8
0
-
-
Max.
2.3
0
Vcc+0.3
0.4
Unit
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
2. Undershoots are sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Vcc = 1.7V~2.3V, T
A
= 0°C to 70°C / -40°C to 85°C (I)
Sym
Parameter
Test Condition
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS1 = V
IH
or
/
OE
=
V
IH
or /WE = V
IL
Icc
Operating Power Supply
/CS1 = V
IL
, V
IN
= V
IH
or V
IL,
Current
I
I/O =
0mA
I
CC1
Average Operating Current
/CS1 = V
IL,
Min Duty Cycle = 100%
I
I/O =
0mA, V
IN
= V
IH
or V
IL
I
SB
TTL Standby Current
/CS1 = V
IH
(TTL Input)
Min.
-1
-1
-
-
Typ.
-
-
-
-
Max.
1
1
5
25
0.3
Unit
uA
uA
mA
mA
mA
uA
uA
V
V
I
SB1
V
OL
V
OH
Standby Current
(CMOS Input)
Output Low Voltage
Output High Voltage
/CS1
≥
Vcc - 0.2V
I
OL
= 0.1mA
I
OH =
-0.1mA
SL
LL
-
-
-
1.4
-
1
-
1
5
0.4
-
Note : 1.Typical values are at Vcc = 1.8V, T
A
= 25°C
2.Typical values are sampled and not 100% tested.
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance(Add, /CS1, /WE, /OE)
C
OUT
Output Capacitance(I/O)
Note : These parameters are sampled and not 100% tested
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Rev.08 /Jun. 00
3
HY62SF8100 Series
AC CHARACTERISTICS
Vcc=1.7V~2.3V, T
A
= 0°C to 70°C /-40°C to 85°C(I), unless otherwise specified
-12
-15
# Symbol
Parameter
Min.
Max. Min.
Max.
READ CYCLE
1
tRC
Read Cycle Time
120
-
150
-
2
tAA
Address Access Time
-
120
-
150
3
tACS
Chip Select Access Time
-
120
-
150
4
tOE
Output Enable to Output Valid
-
60
-
75
5
tCLZ
Chip Select to Output in Low Z
20
-
20
-
6
tOLZ
Output Enable to Output in Low Z
10
-
10
-
7
tCHZ
Chip Deselection to Output in High Z
0
40
0
50
8
tOHZ
Out Disable to Output in High Z
0
40
0
50
9
tOH
Output Hold from Address Change
15
-
15
-
WRITE CYCLE
10 tWC
Write Cycle Time
120
-
150
-
11 tCW
Chip Selection to End of Write
100
-
120
-
12 tAW
Address Valid to End of Write
100
-
120
-
13 tAS
Address Set-up Time
0
-
0
-
14 tWP
Write Pulse Width
85
-
100
-
15 tWR
Write Recovery Time
0
-
0
-
16 tWHZ
Write to Output in High Z
0
40
0
50
17 tDW
Data to Write Time Overlap
50
-
60
-
18 tDH
Data Hold from Write Time
0
-
0
-
19 tOW
Output Active from End of Write
10
-
10
-
-20
Min
Max.
200
-
-
-
30
15
0
0
30
200
170
170
0
135
0
0
80
0
15
-
200
200
100
-
-
60
60
-
-
-
-
-
-
-
80
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
T
A
= 0°C to 70°C / -40°C to 85°C (I),unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 1.8V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
0.9V
Output Load
CL = 30pF + 1TTL Load
AC TEST LOADS
V
TM
=1.8V
4091 Ohm
D
OUT
CL(1)
3273 Ohm
Note
1. Including jig and scope capacitance
Rev.08 /Jun. 00
4
HY62SF8100 Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tACS
/CS1
tOH
CS2
tCHZ
(3)
/OE
tOE
tOLZ
(3)
Data
Out
tCLZ
(3)
High-Z
Data Valid
tOHZ
(3)
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
Data
Out
Previous Data
Data Valid
tOH
READ CYCLE 3(Note 1,2,4)
/CS1
CS2
tACS
tCLZ
(3)
Data
Out
Data Valid
tCHZ
(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low /CS1 and CS2 are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev.08 /Jun. 00
5
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