CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C419/21/25/29/33
256/512/1K/2K/4K x 9 Asynchronous FIFO
Features
■
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages. There are 256, 512,
1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each
FIFO memory is organized such that the data is read in the same
sequential order that it was written. Full and empty flags are
provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth,
or both. The depth expansion technique steers the control
signals from one device to another in parallel. This eliminates the
serial addition of propagation delays, so that throughput is not
reduced. Data is steered in a similar manner.
The read and write operations may be asynchronous; each can
occur at a rate of 50 MHz. The write operation occurs when the
write (W) signal is LOW. Read occurs when read (R) goes LOW.
The nine data outputs go to the high impedance state when R is
HIGH.
A Half Full (HF) output flag that is valid in the standalone and
width expansion configurations is provided. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it is
activated.
In the standalone and width expansion configurations, a LOW on
the retransmit (RT) input causes the FIFOs to retransmit the
data. Read enable (R) and write enable (W) must both be HIGH
during retransmit, and then R is used to access the data.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology. Input
ESD protection is greater than 2000V and latch up is prevented
by careful layout and guard rings.
Asynchronous First-In First-Out (FIFO) Buffer Memories
❐
256 x 9 (CY7C419)
❐
512 x 9 (CY7C421)
❐
1K x 9 (CY7C425)
❐
2K x 9 (CY7C429)
❐
4K x 9 (CY7C433)
Dual-Ported RAM Cell
High Speed 50 MHz Read and Write Independent of Depth and
Width
Low Operating Power: I
CC
= 35 mA
Empty and Full Flags (Half Full Flag in Standalone)
TTL Compatible
Retransmit in Standalone
Expandable in Width
PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP
Pb-free Packages Available
Pin Compatible and Functionally Equivalent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
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Table 1. Selection Guide
4K x 9
Frequency (MHz)
Maximum Access Time (ns)
I
CC1
(mA)
–10
50
10
35
–15
40
15
35
–20
33.3
20
35
–25
28.5
25
35
–30
25
30
35
–40
20
40
35
–65
12.5
65
35
Cypress Semiconductor Corporation
Document #: 38-06001 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 03, 2009
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CY7C419/21/25/29/33
Maximum Rating
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
[1]
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with Power Applied.. –55
°
C to +125
°
C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Power Dissipation.......................................................... 1.0W
Output Current, into Outputs (LOW)............................ 20 mA
Static Discharge Voltage............................................ >2000V
(per MIL–STD–883, Method 3015)
Latch Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
[2]
0
°
C to + 70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit Current
[5]
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Commercial
Industrial
GND < V
I
< V
CC
R > V
IH
, GND < V
O
< V
CC
V
CC
= Max., V
OUT
= GND
All Speed Grades
Min
2.4
2.0
2.2
[4]
Max
0.4
V
CC
V
CC
0.8
+10
+10
–90
Unit
V
V
V
V
μA
μA
mA
–10
–10
Electrical Characteristics
Over the Operating Range
Parameter
I
CC
I
CC1
I
SB1
I
SB2
Description
Operating Current
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA
f = f
MAX
V
CC
= Max.,
I
OUT
= 0 mA
F = 20 MHz
All Inputs =
V
IH
Min.
Commercial
Industrial
Commercial
–10
–15
–20
–25
Min
Max
85
Min
Max
65
100
35
Min
Max
55
90
35
Min
Max
50
80
35
Unit
mA
Operating Current
35
mA
Standby Current
Power Down Current All Inputs >
V
CC
–0.2V
Commercial
Industrial
Commercial
Industrial
10
5
10
15
5
8
10
15
5
8
10
15
5
8
mA
mA
Notes
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. V
IL
(Min.) = –2.0V for pulse durations of less than 20 ns.
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-06001 Rev. *D
Page 3 of 16
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CY7C419/21/25/29/33
Switching Characteristics
Over the Operating Range
[6, 7]
Parameter
t
RC
t
A
t
RR
t
PR
t
LZR[,8]
t
DVR[8,9]
t
HZR[,8,9]
t
WC
t
PW
t
HWZ[,8]
t
WR
t
SD
t
HD
t
MRSC
t
PMR
t
RMR
t
RPW
t
WPW
t
RTC
t
PRT
t
RTR
t
EFL
t
HFH
t
FFH
t
REF
t
RFF
t
WEF
t
WFF
t
WHF
t
RHF
t
RAE
t
RPE
t
WAF
t
WPF
t
XOL
t
XOH
Description
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read LOW to Low Z
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
Write Pulse Width
Write HIGH to Low Z
Write Recovery Time
Data Setup Time
Data Hold Time
MR Cycle Time
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EF LOW
MR to HF HIGH
MR to FF HIGH
Read LOW to EF LOW
Read HIGH to FF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
Effective Read from Write HIGH
Effective Read Pulse Width After EF HIGH
Effective Write from Read HIGH
Effective Write Pulse Width After FF HIGH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
–10
–15
–20
–25
Min
20
10
10
3
5
Max
10
Min
25
10
15
3
5
Max
15
Min
30
10
20
3
5
Max
20
Min
35
10
25
3
5
Max
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
10
5
10
6
0
20
10
10
10
10
20
10
10
20
20
20
10
10
10
10
10
10
10
10
10
10
10
10
15
15
25
15
5
10
8
0
25
15
10
15
15
25
15
10
15
30
20
5
10
12
0
30
20
10
20
20
30
20
10
25
25
25
15
15
15
15
15
15
15
20
15
20
15
15
15
35
25
5
10
15
0
35
25
10
25
25
35
25
10
30
30
30
20
20
20
20
20
20
20
25
20
25
20
20
18
35
35
35
25
25
25
25
25
25
25
25
25
25
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified I
OL
/I
OH
and 30 pF load capacitance,
as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
7. See the last page of this specification for Group A subgroup testing information.
8. t
HZR
transition is measured at +200 mV from V
OL
and –200 mV from V
OH
. t
DVR
transition is measured at the 1.5V level. t
HWZ
and t
LZR
transition is measured at
±100
mV from the steady state.
9. t
HZR
and t
DVR
use capacitance loading as in part (b) of AC Test Load and Waveforms.
Document #: 38-06001 Rev. *D
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