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PEEL22LV10AZT-25L

Description
EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.170 INCH, LEAD FREE, TSSOP-24
CategoryProgrammable logic devices    Programmable logic   
File Size695KB,10 Pages
ManufacturerDiodes
Websitehttp://www.diodes.com/
Environmental Compliance
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PEEL22LV10AZT-25L Overview

EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.170 INCH, LEAD FREE, TSSOP-24

PEEL22LV10AZT-25L Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerDiodes
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP24,.25
Contacts24
Reach Compliance Codeunknown
ArchitecturePAL-TYPE
maximum clock frequency25 MHz
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Humidity sensitivity level3
Dedicated input times11
Number of I/O lines10
Number of entries22
Output times10
Number of product terms133
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
organize11 DEDICATED INPUTS, 10 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3/3.3 V
Programmable logic typeEE PLD
propagation delay25 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage3.6 V
Minimum supply voltage2.7 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
To find out if the package you need is
Not recommended for New designs -
available, contact Customer Service
contact factory for availability
PEEL™ 22LV10AZ -25
CMOS Programmable Electrically Erasable Logic Device
Features
Low Voltage, Ultra Low Power Operation
- Vcc = 2.7 to 3.6 V
- Icc = 5 µA (typical) at standby
- Icc = 1.5 mA (typical) at 1 MHz
- Meets JEDEC LV Interface Spec (JESD8-A)
- 5 Volt tolerant inputs and I/O’s
CMOS Electrically Erasable Technology
- Superior factory testing
-
Reprogrammable in plastic package
-
Reduces retrofit and development costs
Application Versatility
-
Replaces random logic
-
Super set of standard PLDs
-
Pin and JEDEC compatible with 22V10
-
Ideal for battery powered systems
-
Replaces expensive oscillators
Architectural Flexibility
-
Enhanced architecture fits in more logic
-
133 product terms x 44 input AND array
-
12 inputs and 10 I/O pins
-
12 possible macrocell configurations
-
Asynchronous clear, synchronous preset
-
Independent output enables
-
Programmable clock; pin 1 or p-term
-
Programmable clock polarity
-
24 Pin DIP/SOIC/TSSOP and 28 Pin PLCC
-
Schmitt triggers on clock and data inputs
3
Schmitt Trigger Inputs
-
Eliminates external Schmitt trigger devices
- Ideal for encoder designs
General Description
The PEEL™22LV10AZ is a Programmable Electrically Erasable
Logic (PEEL™) SPLD (Simple Programmable Logic Device) that
operates over the supply voltage range of 2.7V-3.6V and fea- tures
ultra-low, automatic “zero” power-down operation. The
PEEL™22LV10AZ is logically and functionally similar to Ana-
chip’s 5V PEEL™22CV10A+ and PEEL™22CV10AZ. The
“zero power” (50 µA max. Icc) power-down mode makes the
PEEL™22LV10AZ ideal for a broad range of battery-powered
portable equipment applications, from hand-held meters to PCM-
CIA modems. EE-reprogrammability provides both the conve-
nience of fast reprogramming for product development and quick
product personalization in manufacturing, including Engineering
Change Orders.
The differences between the PEEL™22LV10AZ and
PEEL™22CV10A include the addition of programmable clock
polarity, p-term clock, and Schmitt trigger input buffers on all
inputs, including the clock. Schmitt trigger inputs allow direct
input of slow signals such as biomedical and sine waves or
clocks. Like the PEEL™22CV10, the PEEL™22LV10AZ is a pin
and JEDEC compatible, logical superset of the industry stan- dard
PAL22V10 SPLD (Figure 26). The PEEL™22LV10AZ pro- vides
additional architectural features that allow more logic to be
incorporated into the design. The PEEL™22LV10AZ architec-
ture allows it to replace over twenty standard 24-pin DIP, SOIC,
TSSOP and PLCC packages.
Figure 26 Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Figure 26 Block Diagram
DIP
TSSOP
PLCC
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10

PEEL22LV10AZT-25L Related Products

PEEL22LV10AZT-25L PEEL22LV10AZS-25L PEEL22LV10AZP-25L PEEL22LV10AZJ-25L PEEL22LV10AZJ-25 PEEL22LV10AZT-25 PEEL22LV10AZS-25 PEEL22LV10AZP-25
Description EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.170 INCH, LEAD FREE, TSSOP-24 EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.300 INCH, LEAD FREE, SOIC-24 EE PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, LEAD FREE, PLASTIC, DIP-24 EE PLD, 25ns, PAL-Type, CMOS, PQCC28, LEAD FREE, PLASTIC, LCC-28 EE PLD, 25ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28 EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.170 INCH, TSSOP-24 EE PLD, 25ns, PAL-Type, CMOS, PDSO24, 0.300 INCH, SOIC-24 EE PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
Is it Rohs certified? conform to conform to conform to conform to incompatible incompatible incompatible incompatible
Maker Diodes Diodes Diodes Diodes Diodes Diodes Diodes Diodes
Parts packaging code TSSOP SOIC DIP QLCC QLCC TSSOP SOIC DIP
package instruction TSSOP, TSSOP24,.25 SOP, SOP24,.4 DIP, DIP24,.3 LEAD FREE, PLASTIC, LCC-28 QCCJ, LDCC28,.5SQ TSSOP, TSSOP24,.25 SOP, SOP24,.4 DIP, DIP24,.3
Contacts 24 24 24 28 28 24 24 24
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown
Architecture PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE
maximum clock frequency 25 MHz 25 MHz 25 MHz 25 MHz 25 MHz 25 MHz 25 MHz 25 MHz
JESD-30 code R-PDSO-G24 R-PDSO-G24 R-PDIP-T24 S-PQCC-J28 S-PQCC-J28 R-PDSO-G24 R-PDSO-G24 R-PDIP-T24
JESD-609 code e3 e3 e3 e3 e0 e0 e0 e0
length 7.8 mm 15.4 mm 31.75 mm 11.5062 mm 11.5062 mm 7.8 mm 15.4 mm 31.75 mm
Dedicated input times 11 11 11 11 11 11 11 11
Number of I/O lines 10 10 10 10 10 10 10 10
Number of entries 22 22 22 22 22 22 22 22
Output times 10 10 10 10 10 10 10 10
Number of product terms 133 133 133 133 133 133 133 133
Number of terminals 24 24 24 28 28 24 24 24
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
organize 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O 11 DEDICATED INPUTS, 10 I/O
Output function MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP DIP QCCJ QCCJ TSSOP SOP DIP
Encapsulate equivalent code TSSOP24,.25 SOP24,.4 DIP24,.3 LDCC28,.5SQ LDCC28,.5SQ TSSOP24,.25 SOP24,.4 DIP24,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR SQUARE SQUARE RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE IN-LINE CHIP CARRIER CHIP CARRIER SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE IN-LINE
Peak Reflow Temperature (Celsius) 260 260 260 260 235 NOT SPECIFIED 245 245
power supply 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V 3/3.3 V
Programmable logic type EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD
propagation delay 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum supply voltage 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
Nominal supply voltage 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V
surface mount YES YES NO YES YES YES YES NO
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) Tin (Sn) Matte Tin (Sn) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING THROUGH-HOLE J BEND J BEND GULL WING GULL WING THROUGH-HOLE
Terminal pitch 0.65 mm 1.27 mm 2.54 mm 1.27 mm 1.27 mm 0.65 mm 1.27 mm 2.54 mm
Terminal location DUAL DUAL DUAL QUAD QUAD DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED 40 40 40 10 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 4.4 mm 7.5 mm 7.62 mm 11.5062 mm 11.5062 mm 4.4 mm 7.5 mm 7.62 mm
Maximum seat height 1.1 mm 2.64 mm - 4.369 mm 4.369 mm 1.1 mm 2.64 mm -
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