The PEEL™22LV10AZ is a Programmable Electrically Erasable
Logic (PEEL™) SPLD (Simple Programmable Logic Device) that
operates over the supply voltage range of 2.7V-3.6V and fea- tures
ultra-low, automatic “zero” power-down operation. The
PEEL™22LV10AZ is logically and functionally similar to Ana-
chip’s 5V PEEL™22CV10A+ and PEEL™22CV10AZ. The
“zero power” (50 µA max. Icc) power-down mode makes the
PEEL™22LV10AZ ideal for a broad range of battery-powered
portable equipment applications, from hand-held meters to PCM-
CIA modems. EE-reprogrammability provides both the conve-
nience of fast reprogramming for product development and quick
product personalization in manufacturing, including Engineering
Change Orders.
The differences between the PEEL™22LV10AZ and
PEEL™22CV10A include the addition of programmable clock
polarity, p-term clock, and Schmitt trigger input buffers on all
inputs, including the clock. Schmitt trigger inputs allow direct
input of slow signals such as biomedical and sine waves or
clocks. Like the PEEL™22CV10, the PEEL™22LV10AZ is a pin
and JEDEC compatible, logical superset of the industry stan- dard
PAL22V10 SPLD (Figure 26). The PEEL™22LV10AZ pro- vides
additional architectural features that allow more logic to be
incorporated into the design. The PEEL™22LV10AZ architec-
ture allows it to replace over twenty standard 24-pin DIP, SOIC,
TSSOP and PLCC packages.
Figure 26 Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
™
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Figure 26 Block Diagram
DIP
TSSOP
PLCC
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
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Rev. 1.0 Dec 16, 2004
Function Description
The PEEL™22LV10AZ implements logic functions as sum-of-
products expressions in a programmable-AND/fixed-OR logic
array. User-defined functions are created by programming the
connections of input signals into the array. User-configurable
output structures in the form of I/O macrocells further increase
logic flexibility.
PEEL™ device programmers automatically program all of the
connections on unused product terms so that they will have no
effect on the output function).
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides com-
3
plete control over the architecture of each output. The ability to
configure each output independently lets you to tailor the config-
uration of the PEEL™22LV10AZ to the precise requirements of
your design.
Architecture Overview
The PEEL™22LV10AZ architecture is illustrated in the block
diagram of Figure 26. Twelve dedicated inputs and 10 I/Os pro-
vide up to 22 inputs and 10 outputs for creation of logic func- tions.
At the core of the device is a programmable electrically- erasable
AND array that drives a fixed OR array. With this struc- ture, the
PEEL™22LV10AZ can implement up to 10 sum-of- products
logic expressions.
Associated with each of the ten OR functions is an I/O macrocell
that can be independently programmed to one of 12 different
configurations, including the four standard 22V10 modes. The
programmable macrocells allow each I/O to be used to create
sequential or combinatorial logic functions of active-high or
active-low polarity, while providing three different feedback
paths into the AND array.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 27, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of
each macrocell is determined by the four EEPROM bits control-
ling these multiplexers. These bits determine output polarity, out-
put type (registered or non-registered) and input-feedback path
(bidirectional I/O, combinatorial feedback). Refer to Table 1 for
details.
Equivalent circuits for the twelve macrocell configurations are
illustrated in Figure 1. In addition to emulating the four PAL-type
output structures (configurations 3, 4, 9, and 10), the macrocell
provides eight additional configurations. When creating a
PEEL™ device design, the desired macrocell configuration is
generally specified explicitly in the design file. When the design is
assembled or compiled, the macrocell configuration bits are
defined in the last lines of the JEDEC programming file.
AND/OR Logic Array
The programmable AND array of the PEEL™22LV10AZ
(shown in Figure 3) is formed by input lines intersecting product
terms. The input lines and product terms are used as follows:
44 Input Lines:
– 24 input lines carry the true and complement of the signals
applied to the 12 input pins
– 20 additional lines carry the true and complement values of
feedback or input signals from the 10 I/Os
133 Product Terms:
– 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and
16) are used to form sum of product functions
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not there is a
logical connection at that intersection. Each product term is
essentially a 44-input AND gate. A product term that is con-
nected to both the true and complement of an input signal will
always be FALSE and thus will not affect the OR function that it
drives. When all the connections on a product term are opened, a
“don’t care” state exists and that term will always be TRUE. When
programming the PEEL™22LV10AZ, the device pro- grammer
first performs a bulk erase to remove the previous pat- tern. The
erase cycle opens every logical connection in the array. The device
is configured to perform the user-defined function by
programming selected connections in the AND array. (Note that
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Output Type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (regis-
tered function). The D-type flip-flop latches data on the rising
edge of the clock and is controlled by the global preset and clear
terms. When the synchronous preset term is satisfied, the Q out-
put of the register is set HIGH at the next rising edge of the clock
input. Satisfying the asynchronous clear sets Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously, the clear
will override the preset.
Output Polarity
Each macrocell can be configured to implement active-high or
active-low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled
under the control of its associated programmable output enable
product term. When the logical conditions programmed on the
output enable term are satisfied, the output signal is propagated to
the I/O pin. Otherwise, the output buffer is switched into the
high-impedance state.
Under the control of the output enable term, the I/O pin can func-
tion as a dedicated input, a dedicated output, or a bi-directional I/ O.
Opening every connection on the output enable term will per-
manently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will
Rev. 1.0 Dec 16, 2004
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always be logically false and the I/O will function as a dedicated
input.
Operates in both 3 Volt and 3.3 Volt Systems
The PEEL™22LV10AZ is designed to operate with a V
CC
range of
2.7 to 3.6 Volts D.C. This allows operation in both 3 Volt
±10% (battery operated) and 3.3 Volt ±10% (power supply oper-
ated) systems. The propagation delay t
PD
is 5 ns slower at the
lower voltage, but this is typically not an issue in battery-oper-
ated systems (see “A.C. Electrical Characteristics” on page 64).
Input/Feedback Select
The PEEL™22LV10AZ macrocell also provides control over the
feedback path. The input/feedback signal associated with each I/ O
macrocell can be obtained from three different locations; from the
I/O input pin, from the Q output of the flip-flop (registered
feedback), or directly from the OR gate (combinatorial feed-
back).
Zero Power Feature
The CMOS PEEL™22LV10AZ features “Zero-Power” standby
operation for ultra-low power consumption. With the “Zero-
Power” feature, transition-detection circuitry monitors the inputs,
I/Os (including CLK) and feedbacks. If these signals do not
change for a period of time greater than approximately two t
PD
’s,
the outputs are latched in their current state and the device auto-
matically powers down. When the next signal transition is
detected, the device will “wake up” for active operation until the
signals stop switching long enough to trigger the next power-
down. (Note that the tPD is approximately 5 ns. slower on the first
transition from sleep mode.)
As a result of the “Zero-Power” feature, significant power sav-
ings can be realized for combinatorial or sequential operations
when the inputs or clock change at a modest rate. See Figure 28.
When the PEEL™22LV10AZ is powered up, a built-in feature
holds the outputs in tri-state until Vcc reaches 2.2V. This pre-
vents output transitions during power-up.
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when using the
pin as a dedicated input or as a bi-directional I/O. (Note that it is
possible to create a registered output function with a bi-direc-
tional I/O, refer to Figure 27).
Combinatorial Feedback
The signal-select multiplexer gives the macrocell the ability to
feedback the output of the OR gate, bypassing the output buffer,
regardless of whether the output function is registered or combi-
natorial. This feature allows the creation of asynchronous latches,
even when the output must be disabled. (Refer to configurations
5, 6, 7, and 8 in Figure 1.)
Registered Feedback
Feedback also can be taken from the register, regardless of
whether the output function is programmed to be combinatorial or
registered. When implementing a combinatorial output func- tion,
registered feedback allows for the internal latching of states
without giving up the use of the external output.
Figure 28 Typical ICC vs. Input Clock Frequency
for the 22LV10AZ
Figure 27 Block Diagram of the
PEEL™22LV10AZ I/O Macrocell
Programmable Clock Options
A unique feature of the PEEL™22LV10AZ is a programmable
clock multiplexer that allows the user to select true or comple-
ment forms of either input pin or product-term clock sources.
100
10
ICC
in
1
mA
0.1
AC = Asynchronous Clear
SP = Synchronous Preset
0.01
0.01
0.1
1
10
100
Frequency in MHz
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Rev. 1.0 Dec 16, 2004
Figure 1 Equivalent Circuits for the Twelve Configurations of the PEEL™22LV10AZ+ I/O Macrocell
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