PALCE22V10H-7JC/5 datasheet, PDF

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PALCE22V10H-7JC/5: DescriptionEE PLD, 7.5ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28; CategoryProgrammable logic devices Programmable logic; File Size236KB，27 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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PALCE22V10H-7JC/5 Overview

EE PLD, 7.5ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28

PALCE22V10H-7JC/5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	QLCC
package instruction	QCCJ, LDCC28,.5SQ
Contacts	28
Reach Compliance Code	unknown
Other features	10 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 1 EXTERNAL CLOCK
Architecture	PAL-TYPE
maximum clock frequency	111 MHz
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.5062 mm
Humidity sensitivity level	1
Dedicated input times	11
Number of I/O lines	10
Number of entries	22
Output times	10
Number of product terms	132
Number of terminals	28
Maximum operating temperature	75 °C
Minimum operating temperature
organize	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	EE PLD
propagation delay	7.5 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.5062 mm

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FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25

IND: H-10/15/20/25

PALCE22V10 Family

24-Pin EE CMOS Versatile PAL Device

DISTINCTIVE CHARACTERISTICS

As fast as 5-ns propagation delay and

142.8 MHz f

MAX

(external)

Low-power EE CMOS

10 macrocells programmable as registered or

combinatorial, and active high or active low to

match application needs

Varied product term distribution allows up to

16 product terms per output for complex

functions

Peripheral Component Interconnect (PCI)

compliant (-5/-7/-10)

Global asynchronous reset and synchronous

preset for initialization

Power-up reset for initialization and register

preload for testability

Extensive third-party software and programmer

support through FusionPLD partners

24-pin SKINNYDIP, 24-pin SOIC, 24-pin Flat-

pack and 28-pin PLCC and LCC packages save

space

5-ns and 7.5-ns versions utilize split lead-

frames for improved performance

GENERAL DESCRIPTION

The PALCE22V10 provides user-programmable logic

for replacing conventional SSI/MSI gates and flip-flops

at a reduced chip count.

The PAL device implements the familiar Boolean logic

transfer function, the sum of products. The PAL device

is a programmable AND array driving a fixed OR array.

The AND array is programmed to create custom product

terms, while the OR array sums selected terms at the

outputs.

The product terms are connected to the fixed OR array

with a varied distribution from 8 to16 across the outputs

(see Block Diagram). The OR sum of the products feeds

the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial, and active

high or active low. The output configuration is

determined by two bits controlling two multiplexers in

each macrocell.

AMD’s FusionPLD program allows PALCE22V10 de-

signs to be implemented using a wide variety of popular

industry-standard design tools. By working closely with

the FusionPLD partners, AMD certifies that the tools

provide accurate, quality support. By ensuring that third-

party tools are available, costs are lowered because a

designer does not have to buy a complete set of new

tools for each device. The FusionPLD program also

greatly reduces design time since a designer can use a

tool that is already installed and familiar.

BLOCK DIAGRAM

CLK/I

- I

Programmable

AND Array

(44 x 132)

RESET

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

OUTPUT

LOGIC

MACRO

CELL

PRESET

I/O

16564D-1

Publication#

16564

Rev.

Issue Date:

February 1996

Amendment

2-217

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