EE PLD, 25ns, PAL-Type, CMOS, PDIP24
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Lattice |
| package instruction | DIP, DIP24,.3 |
| Reach Compliance Code | not_compliant |
| Architecture | PAL-TYPE |
| maximum clock frequency | 33.3 MHz |
| JESD-30 code | R-PDIP-T24 |
| JESD-609 code | e0 |
| Number of entries | 22 |
| Output times | 10 |
| Number of product terms | 132 |
| Number of terminals | 24 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | -40 °C |
| Output function | MACROCELL |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP24,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| power supply | 5 V |
| Programmable logic type | EE PLD |
| propagation delay | 25 ns |
| Certification status | Not Qualified |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | INDUSTRIAL |
| Terminal surface | Tin/Lead (Sn85Pb15) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
京公网安备 11010802033920号
EEWORLD
