PALCE22V10Q-25JC/4 datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> PALCE22V10Q-25JC/4

PALCE22V10Q-25JC/4: DescriptionEE PLD, 25 ns, PQCC28, PLASTIC, LCC-28; CategoryProgrammable logic devices Programmable logic; File Size1MB，35 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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PALCE22V10Q-25JC/4 Overview

EE PLD, 25 ns, PQCC28, PLASTIC, LCC-28

PALCE22V10Q-25JC/4 Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
Parts packaging code	QLCC
package instruction	QCCJ,
Contacts	28
Reach Compliance Code	unknown
Other features	10 MACROCELLS, 1 EXTERNAL CLOCK, SHARED INPUT/CLOCK, VARIABLE PRODUCT TERMS
maximum clock frequency	33.3 MHz
JESD-30 code	S-PQCC-J28
length	11.5062 mm
Dedicated input times	11
Number of I/O lines	10
Number of terminals	28
Maximum operating temperature	75 °C
Minimum operating temperature
organize	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	COMMERCIAL
Maximum seat height	4.572 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	NOT SPECIFIED
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.5062 mm

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PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25

PALCE22V10Z COM'L: -25

IND: -15/25

PALCE22V10 and PALCE22V10Z

Families

24-Pin EE CMOS (Zero Power) Versatile PAL Device

DISTINCTIVE CHARACTERISTICS

As fast as 5-ns propagation delay and 142.8 MHz f

MAX

(external)

Low-power EE CMOS

10 macrocells programmable as registered or combinatorial, and active high or active low to

match application needs

Varied product term distribution allows up to 16 product terms per output for complex

functions

Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)

Global asynchronous reset and synchronous preset for initialization

Power-up reset for initialization and register preload for testability

Extensive third-party software and programmer support

24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC

5-ns and 7.5-ns versions utilize split leadframes for improved performance

GENERAL DESCRIPTION

The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and

ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z is an advanced PAL

device built with zero-power, high-speed, electrically-

erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-

power CMOS SSI/MSI gates and ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby

current, the PALCE22V10Z allows battery-powered operation for an extended period.

The PAL device implements the familiar Boolean logic transfer function, the sum of products. The

PAL device is a programmable AND array driving a ﬁxed OR array. The AND array is programmed

to create custom product terms, while the OR array sums selected terms at the outputs.

The product terms are connected to the ﬁxed OR array with a varied distribution from 8 to16 across

the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each

macrocell can be programmed as registered or combinatorial, and active-high or active low. The

output conﬁguration is determined by two bits controlling two multiplexers in each macrocell.

Publication#

16564

Amendment/0

Rev:

Issue Date:

November 1998

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