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SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
D
D
D
D
D
D
D
D
D
D
D
D
D
D
>400 Mbps (200 MHz) Signaling Rates
Flow-Through Pinout Simplifies PCB
Layout
50 ps Channel-to-Channel Skew (Typ)
200 ps Differential Skew (Typ)
Propagation Delay Times 2.7 ns (Typ)
3.3 V Power Supply Design
High-Impedance LVDS Inputs on Power
Down
Low-Power Dissipation (40 mW at 3.3 V
Static)
Accepts Small Swing (350 mV) Differential
Signal Levels
Supports Open, Short, and Terminated
Input Fail-Safe
Industrial Operating Temperature Range
(–40°C to 85°C)
Conforms to TIA/EIA-644 LVDS Standard
Available in SOIC and TSSOP Packages
Pin-Compatible With DS90LV048A From
National
NOT RECOMMENDED FOR NEW DESIGNS
For Replacement Use SN65LVDS048A
D OR PW PACKAGE
(TOP VIEW)
R
IN1–
R
IN1+
R
IN2+
R
IN2–
R
IN3–
R
IN3+
R
IN4+
R
IN4–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
R
OUT1
R
OUT2
V
CC
GND
R
OUT3
R
OUT4
EN
functional diagram
EN
EN
R
IN1+
R
IN1–
R
IN2+
R
IN2–
R
IN3+
R
IN3–
R
IN4+
R
IN4–
R1
R
OUT1
description
The SN65LVDS048 is a quad differential line receiver
that implements the electrical characteristics of
low-voltage differential signaling (LVDS). This signaling
technique lowers the output voltage levels of 5-V
differential standard levels (such as EIA/TIA-422B) to
reduce the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the quad
differential receivers will provide a valid logical output
state with a
±100-mV
differential input voltage within the
input common-mode voltage range. The input
common-mode voltage range allows 1 V of ground
potential difference between two LVDS nodes.
R2
R
OUT2
R3
R
OUT3
R4
R
OUT4
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100
Ω.
The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS048 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2000, Texas Instruments Incorporated
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1
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
TRUTH TABLE
DIFFERENTIAL INPUT
RIN+ – RIN–
VID
≥
100 mV
VID
≤
–100 mV
Open/short or terminated
X
ENABLES
EN
H
EN
L or OPEN
OUTPUT
ROUT
H
L
H
All other conditions
Z
H = high level, L = low level, X = irrelevant, Z = high impedance (off)
equivalent input and output schematic diagrams
VCC
VCC
VCC
50
Ω
300 kΩ
300 kΩ
EN,EN
5
Ω
Output
7V
Input
7V
7V
Input
300 kΩ
7V
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range (V
CC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Input voltage range, V
I
(R
IN+
, R
IN–
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Enable input voltage (EN, EN ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
CC
+0.3 V)
Output voltage, V
O
(R
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
CC
+0.3 V)
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
D
PW
TA
≤
25°C
POWER RATING
950 mW
774 mW
OPERATING FACTOR‡
ABOVE TA = 25°C
7.6 mW/°C
6.2 mW/°C
TA = 85°C
POWER RATING
494 mW
402 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
2
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SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
recommended operating conditions
MIN
Supply voltage, VCC
Receiver input voltage
Common–mode input voltage, VIC
|V
|
2.4
3
GND
ID
2
NOM
3.3
MAX
3.6
3
ID
*
|V2 |
UNIT
V
V
V
°C
Operating free-air temperature, TA
–40
25
VCC – 0.8
85
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 2)
PARAMETER
VIT+
VIT–
V(CMR)
IIN
Differential input high threshold voltage
Differential input low threshold voltage
Common mode voltage range
Input current
TEST CONDITIONS
,
,
VCM = 1.2 V, 0.05 V, 2.35 V
(see Note 3)
VID = 200 mV pk to pk (see Note 4)
VIN = 2.8 V
VCC = 3.6 V or 0 V
36
VIN = 0 V
VIN = 3.6 V
VCC = 0 V
IOH = –0.4 mA, VID = 200 mV
IOH = –0.4 mA, input terminated
IOH = –0.4 mA, input shorted
IOL = 2 mA, VID = –200 mV
Enabled, VOUT = 0 V (see Note 5)
Disabled, VOUT = 0 V or VCC
–1
2.0
GND
VIN = 0 V or VCC,
Other input = VCC or GND
ICL = –18 mA
EN = VCC,
Inputs open
–10
–1.5
–0.8
8
15
MIN
–100
0.1
–20
–20
–20
2.7
2.7
2.7
±1
±1
±1
3.2
3.2
3.2
0.05
–65
0.25
–100
1
VCC
0.8
10
2.3
20
20
20
TYP†
MAX
100
UNIT
mV
V
µA
µA
µA
V
V
V
V
mA
µA
V
V
µA
V
mA
VOH
VOL
IOS
IO(Z)
VIH
VIL
II
VIK
ICC
Output high voltage
Output low voltage
Output short circuit current
Output 3-state current
Input high voltage
Input low voltage
Input current (enables)
Input clamp voltage
No load supply current, receivers enabled
ICC(Z)
No load supply current, receivers disabled
EN = GND,
Inputs open
0.6
1.5
mA
† All typical values are at 25°C and with a 3.3-V supply.
NOTES: 2. Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground,
unless otherwise specified.
3. VCC is always higher than RIN+ and RIN– voltage, RIN– and RIN+ have a voltage range of –0.2 V to VCC–VID/2. To be compliant with
ac specifications the common voltage range is 0.1 V to 2.3 V.
4. The VCMR range is reduced for larger VID, Example: If VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs
shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external
common-mode voltage applied. A VID up to VCC–0 V may be applied to the RIN+ and RIN– inputs with the common-mode voltage
set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew
specifications apply for 200 mV < VID < 800 mV over the common-mode range.
5. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be
shorted at a time. Do not exceed maximum junction temperature specification.
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3
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Notes 6)
PARAMETER
tPHL
tPLH
tSK(p)
tSK(o)
tSK(pp)
tSK(lim)
tr
tf
tPHZ
tPLZ
tPZH
tPZL
Differential propagation delay, high-to-low
Differential propagation delay, low-to-high
Differential pulse skew (tPHLD – tPLHD) (see Note 7)
Differential channel-to-channel skew; same device (see Note 8)
Differential part-to-part skew (see Note 9)
Differential part-to-part skew (see Note10)
Rise time
Fall time
Disable time high to Z
Disable time low to Z
Enable time Z to high
Enable time Z to low
RL = 2 K
Ω
F
CL = 15 pF
(
g
(see Figure 3 and 4 )
0.5
0.5
8
6
8
7
CL = 15 pF
VID = 200 mV
(see Figure 1 and 2 )
TEST CONDITIONS
MIN
1.9
1.9
TYP†
2.7
2.9
200
50
MAX
3.7
3.7
450
500
1
1.5
1
1
9
8
10
8
UNIT
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
f(MAX)
Maximum operating frequency (see Note 11)
All channels switching
200
250
MHz
† All typical values are at 25°C and with a 3.3-V supply.
NOTES: 6. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50
Ω,
tr and tf (0% – 100%)
≤
3 ns for RIN.
7. tSK(p)|tPLH – tPHL| is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
8. tSK(o) is the differential channel-to-channel skew of any event on the same device.
9. tSK(pp) is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified
differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the
operating temperature range.
10. tsk(lim) part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to
devices over recommended operating temperature and voltage ranges, and across process distribution. tsk(lim) is defined as |Min
– Max| differential propagation delay.
11. f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%,
VOD > 250 mV, all channels switching
4
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