PEEL18CV8JI-25 datasheet, PDF - EEWORLD Datasheet

PEEL18CV8JI-25: DescriptionEE PLD, 25ns, PAL-Type, CMOS, PQCC20, PLASTIC, LCC-20; CategoryProgrammable logic devices Programmable logic; File Size461KB，8 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PEEL18CV8JI-25 Overview

EE PLD, 25ns, PAL-Type, CMOS, PQCC20, PLASTIC, LCC-20

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	QLCC
package instruction	QCCJ, LDCC20,.4SQ
Contacts	20
Reach Compliance Code	unknown
Other features	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	28.5 MHz
JESD-30 code	S-PQCC-J20
JESD-609 code	e0
length	8.9662 mm
Dedicated input times	9
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	74
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	9 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	4.369 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	8.9662 mm

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