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STRUCTURE
TYPE
PRODUCT SERIES
FEATURES
Silicon Monolithic Integrated Circuit
0.3A Low Dropout Voltage Regulator with Shut Down Switch（Adjustable Voltage）
ＢＡ３６６２ＣＰ‐Ｖ５
Maximum Output Current : 300½A
High Input Voltage : 35V, Built in Over Voltage Protection
○ABSOLUTE
MAXIMUM RATINGS（Ta=25℃）
Parameter
Symbol
Supply Voltage
Vcc
Output Control Voltage
V
CTL
Power Dissipation
Pd
(TO220CP-V5)
Operating Temperature Range
Topr
Storage Temperature Range
Tstg
Maximum Junction Temperature
Tjmax
Peak Supply Voltage
Vcc peak
Limits
-0.3
½
+35
-0.3
½
Vcc
2000
-40
½
+125
-55
½
+150
150
50
※1
Unit
V
V
mW
℃
℃
℃
V
※2
※3
※1
Do not however exceed Pd.
※2
Derating in done at 16mW/℃ for operating above Ta≧25℃.（without heat sink）
※3
Bias voltage in 200msec (tr≧1msec).
○OPERATING
CONDITIONS（Ta=-40½+125℃, however do not exceed Pd.）
Parameter
Symbol
Min.
Supply Voltage
Output Current
Output Voltage
○PROTECTION（Design
Guarantee）
Parameter
Over Voltage Protection
Symbol
Vcc
Min.
26
Typ.
28
Vcc
Io
Vo
4.0
－
3
Max.
25.0
0.3
15
Unit
V
A
V
Max.
30
Unit
V
NOTE : This product is not designed for protection against radioactive rays.
REV.
Ａ
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○ELECTRICAL
CHARACTERISTIC
（Unless
otherwise specified, Ta=25℃、Vcc=10V、V
CTL
=5V、Io=200mA、Vo=5V Setting）
Limit
Parameter
Symbol
Umit
Conditions
Min.
Typ.
Max.
Shut Down Current
Isd
－
0
10
μA
V
CTL
=0V
Bias Current
Ib
－
2.5
5.0
mA V
CTL
=2V, Io=0mA
Ｃ
Terminal Voltage
Vc
1.200
1.225
1.250
V
Io=50mA
⊿Vd
－
Vcc=Vo×0.95
Dropout Voltage
0.3
0.5
V
Peak Output Current
Io
0.3
－
－
A
f=120Hz,ein
※
1
=1Vrms,
Ripple Rejection
R.R.
45
55
－
dB
Io=100mA
Line Regulation
Reg.I
－
20
100
mV Vcc=6→25V
－
Load Regulation
Reg.L
40
80
mV Io=5mA→200mA
Temperature Coefficient
Tcvo
－
±0.02
－
％/℃
Io=5mA,Tj=0½125℃
of Output Current
Output Short Current
Ios
－
0.1
－
A
Vcc=25V,Vo=0V
ON Mode Voltage
VthH
2.0
－
－
V
ACTIVE MODE, Io=0mA
－
－
OFF Mode Voltage
VthL
0.8
V
OFF MODE, Io=0mA
Input High Current
I
CTL
100
200
300
μA
V
CTL
=5V, Io=0mA
※1
ein : Input Voltage Ripple
○PHYSICAL
DIMENSIONS, MARKING
Marking
BA3662
Lot. No.
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○
BLOCK DIAGRAM
○PIN
NO. , PIN NAME
Pin Number
Vref
Driver
Pin Name
CTL
Vcc
GND
V
O
C
1
2
4
Vcc
2
V
O
3
4
5
OVP
TSD
OCP
1
3
CTL
GND
5
C
○NOTES
FOR USE
1. Absolute maximum range
Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed we cannot be defined the failure mode,
such as short mode or open mode.
Therefore physical security countermeasure, like fuse, is to be given when a specific mode to be beyond absolute maximum ratings is
considered.
2. Electrical characteristics described in these specifications may vary, depending on temperature, supply voltage, external circuits
and other conditions. Therefore, be sure to check all relevant factors, including transient characteristics.
3. GND pin voltage
GND terminal should be connected the lowest voltage, under all conditions. And all terminals except GND should be under GND terminal
voltage under all conditions including transient situations.
4. GND pattern
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming from the
wiring resistance and high current does not cause any voltage change in the small-signal GND. In the same way, care must be taken
to avoid voltage fluctuations in any connected external component GND.
5. Be sure to connect a capacitor with capacitance of at least 22μF, including temperature characteristics and variation, to prevent
oscillation between the Vo and GND. Note that if the capacity of the capacitor changes due to factors such as changes in temperature
or ESR, oscillation may occur, and the original characteristics of the IC may not be realized. For example, when a ceramic capacitor
is employed, oscillation will be generated because the series resistance is too small. Please take countermeasures to prevent this,
such as adding a series resistor. Standard electrolytic capacitors are subject to extremely large capacitance and ESR fluctuations due
to temperature conditions. Particularly at low temperature, capacity is decreased, while ESR grows larger, conditions which increase
the vulnerability to oscillation. Therefore, be certain to check for the presence of oscillation.
Keep capacitor capacitance within a range of 22μF½1000μF. It is also recommended that a 0.33μF bypass capacitor be
connected as close to the input pin-GND as location possible. However, in situations such as rapid fluctuation of the input voltage or
the load, please check the operation in real application to determine proper capacitance.
6. Mounting Failures
Mounting failure, such as misdirection or mismount, may cause a malfunction in the device.
7.
Malfunction may be happened when the device is used in the strong electromagnetic field.
8. Precautions for board inspection
Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be certain to use
proper discharge procedure before each process of the test operation. To prevent electrostatic accumulation and discharge in the
assembly process, thoroughly ground yourself and any equipment that could sustain ESD damage, and continue observing
ESD-prevention procedures in all handling, transfer and storage operations. Before attempting to connect components to the test
setup, make certain that the power supply is OFF. Likewise, be sure the power supply is OFF before removing any component
connected to the test setup.
9. Power dissipation
If IC is used on condition that the power loss is over the power dissipation, the reliability will become worse by heat up. The power
dissipation that is described to the absolute maximum rating in this specification is a value when the heat sink is not populated. In this case
it exceed the power dissipation, please consider using the heat sink,etc.
Also, be sure to use this IC within a power dissipation range allowing enough of margin.
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10. Thermal design
Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions.
11. Over current protection circuit
（OCP）
The built-in over current protection circuit is designed to respond to the output current and prevent destruction of the IC from load
short circuits; however, it is only effective in protecting the IC from destruction in sudden over current accidents. The protection
circuit is not to be used continuously, or for transitions. In executing thermal design, bear in mind that over current protection has
negative characteristic according with the temperature.
12. Thermal shutdown circuit
（TSD）
A built-in internal shutdown circuit is provided to protect the IC from heat destruction. Operation has to be done within the allowable
loss range, but in continuous use beyond the range, chip temperature Tj will increase to the threshold, activating the TSD circuit and
turning the output power Tr OFF. Once the chip temperature Tj returns to the normal range, the circuit is automatically restored. Note
that the TSD circuit is designed to operate over the maximum absolute rating. Therefore, make absolutely certain not to use the TSD
function in set design.
13. Internal circuits or elements may be damaged when Vcc and pin voltage are reversed. For example, Vcc short circuit to GND
while a external capacitor is charged. Output pin capacitor is recommended no larger than 1000μF. In addition, inserting a Vcc
series countercurrent prevention diode, or a bypass diode between the various pins and the vcc, is recommended.
14. Positive voltage surges on Vcc pin
A power zener diode should be inserted between Vcc and GND for protection against voltage surges of more than 50V on the Vcc
pin.
15. Negative voltage surges on Vcc pin
A schottky barrier diode should be inserted between Vcc and GND for protection against voltages lower than GND on the Vcc pin.
16. We recommend to put Diode for protection purpose in case of output pin connected with large load of impedance or reserve
current occurred at initial and output off.
17. Regarding input pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN
junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or
transistors. For example (refer to the figure below):
●When
GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
●When
GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such
as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided.
Resistor
(Pin A)
(Pin B)
Transistor (NPN)
B
E
C
(Pin B)
B
N
P+
N
P
N
P
P+
N
Parasitic elements
GND
N
P substrate
(Pin A)
Parasitic elements
or transistors
GND
Parasitic elements
P+
N
N
Parasitic elements
or transistors
P
P+
GND
C
E
Example of Simple Monolithic IC Architecture
REV.
Ａ
Notice
Notes
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The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
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The technical information specified herein is intended only to show the typical functions of and
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