a
FEATURES
Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low Power: 90 mW at 100 MSPS per Channel
On-Chip Reference and Track/Holds
475 MHz Analog Bandwidth Each Channel
SNR = 47 dB @ 41 MHz
1 V p-p Analog Input Range Each Channel
Single +3.0 V Supply Operation (2.7 V–3.6 V)
Standby Mode for Single Channel Operation
Twos Complement or Offset Binary Output Mode
Output Data Alignment Mode
APPLICATIONS
Battery Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications
ENC
A
A
IN
A
A
IN
A
REF
IN
A
REF
OUT
REF
IN
B
A
IN
B
A
IN
B
ENC
B
8-Bit, 40/80/100 MSPS
Dual A/D Converter
AD9288
FUNCTIONAL BLOCK DIAGRAM
V
DD
TIMING
OUTPUT REGISTER
AD9288
T/H
ADC
8
8
D7
A
–D0
A
SELECT #1
SELECT #2
REF
OUTPUT REGISTER
DATA FORMAT
SELECT
8
D7
B
–D0
B
T/H
ADC
8
TIMING
V
D
GND
V
DD
GENERAL DESCRIPTION
The AD9288 is a dual 8-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 100 MSPS conversion rate with out-
standing dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
The encode input is TTL/CMOS compatible and the 8-bit
digital outputs can be operated from +3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combi-
nation of standby modes, digital data formats and digital data
timing schemes. In standby mode, the digital outputs are driven
to a high impedance state.
Fabricated on an advanced CMOS process, the AD9288 is avail-
able in a 48-lead surface mount plastic package (7
×
7 mm,
1.4 mm LQFP) specified over the industrial temperature range
(–40°C to +85°C).
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9288–SPECIFICATIONS
(V
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error
1
Gain Tempco
1
Gain Matching
Voltage Matching
ANALOG INPUT
Input Voltage Range
(With Respect to
AIN)
Common-Mode Voltage
Input Offset Voltage
Reference Voltage
Reference Tempco
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (t
EH
)
Encode Pulsewidth Low (t
EL
)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Output Valid Time (t
V
)
2
Output Propagation Delay (t
PD
)
2
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
DIGITAL OUTPUTS
3
Logic “1” Voltage
Logic “0” Voltage
POWER SUPPLY
Power Dissipation
4
Standby Dissipation
4, 5
Power Supply Rejection Ratio
(PSRR)
DYNAMIC PERFORMANCE
6
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
IN
= 10.3 MHz
f
IN
= 26 MHz
f
IN
= 41 MHz
+25°C
Full
+25°C
Full
Full
+25°C
Full
Full
+25°C
+25°C
I
VI
I
VI
VI
I
VI
VI
V
V
Temp
Test
Level
DD
= 3.0 V; V
D
= 3.0 V, Differential Input; External reference unless otherwise noted.)
AD9288BST-80
Min
Typ
Max
8
+1.25
+1.50
+1.25
+1.50
–6
–8
±
0.5
±
0.50
+1.25
+1.50
+1.25
+1.50
–6
–8
AD9288BST-40
Min
Typ
Max
8
±
0.5
±
0.50
+1.25
+1.50
+1.25
+1.50
Units
Bits
LSB
LSB
LSB
LSB
% FS
% FS
ppm/°C
% FS
mV
AD9288BST-100
Min
Typ
Max
8
±
0.5
±
0.50
–6
–8
Guaranteed
±
2.5
+6
+8
80
±
1.5
±
15
Guaranteed
±
2.5
+6
+8
80
±
1.5
±
15
Guaranteed
±
2.5
+6
+8
80
±
1.5
±
15
Full
Full
+25°C
Full
Full
Full
+25°C
Full
+25°C
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
Full
Full
+25°C
Full
Full
Full
Full
+25°C
+25°C
+25°C
V
V
I
VI
VI
VI
I
VI
V
V
VI
IV
IV
IV
V
V
VI
VI
VI
VI
VI
VI
V
VI
VI
VI
VI
I
V
V
–35
1.2
7
5
±
512
±
200
±
10
±
40
1.25
±
130
10
2
475
+35
1.3
13
16
–35
1.2
7
5
±
512
±
200
±
10
±
40
1.25
±
130
10
2
475
+35
1.3
13
16
–35
1.2
7
5
±
512
±
200
±
10
±
40
1.25
±
130
10
2
475
+35
1.3
13
16
mV p-p
mV
mV
mV
V
ppm/°C
kΩ
kΩ
pF
MHz
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
V
V
µA
µA
pF
V
V
mW
mW
mV/V
ns
ns
100
4.3
4.3
0
5
3.0
4.5
2.0
0.8
±
1
±
1
2.0
2.45
0.05
180
6
8
2
2
218
11
20
1
1000
1000
80
5.0
5.0
0
5
3.0
4.5
2.0
0.8
±
1
±
1
2.0
2.45
0.05
171
6
8
2
2
207
11
20
1
1000
1000
40
8.0
8.0
0
5
3.0
4.5
2.0
0.8
±
1
±
1
2.0
2.45
0.05
156
6
8
2
2
189
11
20
1
1000
1000
+25°C
+25°C
+25°C
I
I
I
44
47.5
47.5
47.0
44
47.5
47
44
47.5
dB
dB
dB
–2–
REV. 0
AD9288
Parameter
Temp
Test
Level
AD9288BST-100
Min
Typ
Max
AD9288BST-80
Min
Typ
Max
AD9288BST-40
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
6
(Continued)
Signal-to-Noise Ratio (SINAD) (With Harmonics)
f
IN
= 10.3 MHz
+25°C I
f
IN
= 26 MHz
+25°C I
f
IN
= 41 MHz
+25°C I
Effective Number of Bits
f
IN
= 10.3 MHz
+25°C I
f
IN
= 26 MHz
+25°C I
+25°C I
f
IN
= 41 MHz
2nd Harmonic Distortion
+25°C I
f
IN
= 10.3 MHz
f
IN
= 26 MHz
+25°C I
+25°C I
f
IN
= 41 MHz
3rd Harmonic Distortion
+25°C I
f
IN
= 10.3 MHz
f
IN
= 26 MHz
+25°C I
+25°C I
f
IN
= 41 MHz
Two-Tone Intermod Distortion (IMD)
f
IN
= 10.3 MHz
+25°C V
44
47
47
47
7.5
7.5
7.5
70
70
70
60
60
60
60
44
47
47
47
7.5
7.5
7.5
70
70
70
60
60
60
60
44
47
dB
dB
dB
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
7.0
7.5
7.0
7.0
55
70
55
55
55
60
55
52
60
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2
t
V
and t
PD
are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 10 pF or a dc current of
±
40
µA.
3
Digital supply current based on V
DD
= +3.0 V output drive with <10 pF loading under dynamic test conditions.
4
Power dissipation measured under the following conditions: f
S
= 100 MSPS, analog input is –0.7 dBFS, both channels in operation.
5
Standby dissipation calculated with encode clock in operation.
6
SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
V
D
, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to V
D
+ 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
D
+ 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Test Level
I
100% production tested.
II 100% production tested at +25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes for
military devices.
Table I. User Select Options
ORDERING GUIDE
S1
Package
Options
ST-48*
Evaluation Board
0
0
1
1
S2
0
1
0
1
User Select Options
Standby Both Channels A and B.
Standby Channel B Only.
Normal Operation (Data Align Disabled).
Data align enabled (data from both channels avail-
able on rising edge of Clock A. Channel B data is
delayed a 1/2 clock cycle).
Model
AD9288BST
-40, -80, -100
AD9288/PCB
Temperature
Ranges
–40°C to +85°C
+25°C
*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7
×
7 mm: LQFP).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9288 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD9288
PIN CONFIGURATION
D7
A
(MSB)
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE
and the instant at which the analog input is sampled.
D6
A
D5
A
D4
A
D3
A
D2
A
D1
A
D0
A
ENC
A
V
DD
GND
V
D
Aperture Uncertainty (Jitter)
48 47 46 45 44 43 42 41 40 39 38 37
The sample-to-sample variation in aperture delay.
36
NC
35
NC
34
GND
33
V
DD
32
GND
GND
1
A
IN
A
2
A
IN
A
3
DFS
4
REF
IN
A
5
REF
OUT 6
REF
IN
B
7
S1
8
S2
9
A
IN
B
10
A
IN
B
11
GND
12
NC = NO CONNECT
Differential Nonlinearity
PIN 1
IDENTIFIER
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
AD9288
TOP VIEW
(Not to Scale)
31
V
D
30
V
D
29
GND
28
V
DD
27
GND
26
NC
25
NC
Pulsewidth high is the minimum amount of time that the EN-
CODE pulse should be left in Logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Integral Nonlinearity
13 14 15 16 17 18 19 20 21 22 23 24
ENC
B
V
DD
GND
D3
B
D2
B
D1
B
(MSB) D7
B
D6
B
D5
B
D4
B
D0
B
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” deter-
mined by a least square curve fit.
Minimum Conversion Rate
V
D
PIN FUNCTION DESCRIPTIONS
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
Pin No.
Name
Description
Ground.
Analog Input for Channel A.
Analog Input for Channel A
(Complementary).
Data Format Select: (Offset
binary output available if set
low. Twos complement output
available if set high).
Reference Voltage Input for
Channel A.
Internal Reference Voltage.
Reference Voltage Input for
Channel B.
User Select #1 (Refer to Table
I), Tied with Respect to V
D
.
User Select #2 (Refer to Table
I), Tied with Respect to V
D
.
Analog Input for Channel B
(Complementary).
Analog Input for Channel B.
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (3 V).
Digital Output for Channel B.
Do Not Connect.
Digital Output for Channel A.
Clock Input for Channel A.
1, 12, 16, 27, 29,
32, 34, 45
GND
2
A
IN
A
3
AINA
4
DFS
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE
and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
5
6
7
8
9
10
11
13, 30, 31, 48
14
15, 28, 33, 46
17–24
25, 26, 35, 36
37–44
47
REF
IN
A
REF
OUT
REF
IN
B
S1
S2
AINB
A
IN
B
V
D
ENC
B
V
DD
D7
B
–D0
B
NC
D0
A
–D7
A
ENC
A
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; re-
ported in dBc.
Two-Tone SFDR
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Worst Harmonic
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
–4–
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
REV. 0
AD9288
SAMPLE N
SAMPLE N+1
SAMPLE N+5
A
IN
A, A
IN
B
t
A
t
EH
t
EL
1/ f
S
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
ENCODE A, B
t
PD
t
V
D7
A
–D0
A
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
DATA N+1
D7
B
–D0
B
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
DATA N+1
Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE N
SAMPLE N+1
SAMPLE N+5
A
IN
A, A
IN
B
t
A
t
EH
t
EL
1/ f
S
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
ENCODE A
ENCODE B
t
PD
t
V
D7
A
–D0
A
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
DATA N+1
D7
B
–D0
B
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
DATA N+1
Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
REV. 0
–5–
RF/Wirelessly
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