MM74HC139 Dual 2-To-4 Line Decoder
September 1983
Revised December 2003
MM74HC139
Dual 2-To-4 Line Decoder
General Description
The MM74HC139 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address
decoding or data routing applications. It possesses the
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds compara-
ble to low power Schottky TTL logic.
The MM74HC139 contain two independent one-of-four
decoders each with a single active low enable input (G1, or
G2). Data on the select inputs (A1, and B1 or A2, and B2)
cause one of the four normally high outputs to go LOW.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent loads, and are functionally as well as pin
equivalent to the 74LS139. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
s
Typical propagation delays —
Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
s
Low power: 40
µ
W quiescent supply power
s
Fanout of 10 LS-TTL devices
s
Input current maximum 1
µ
A, typical 10 pA
Ordering Code:
Order Number
MM74HC139M
(Note 1)
MM74HC139SJ
MM74HC139MTC
(Note 1)
MM74HC139N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Inputs
Enable
G
H
L
L
L
L
H
=
HIGH Level
L
=
LOW Level
X
=
Don't Care
Outputs
Select
B
X
L
L
H
H
A
X
L
H
L
H
Y0
H
L
H
H
H
Y1
H
H
L
H
H
Y2
H
H
H
L
H
Y3
H
H
H
H
L
© 2003 Fairchild Semiconductor Corporation
DS005311
www.fairchildsemi.com
MM74HC139
Logic Diagram
(1 of 2)
www.fairchildsemi.com
2
MM74HC139
Absolute Maximum Ratings
(Note 2)
(Note 3)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 4)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
2
0
Max
6
V
CC
Units
V
V
−
0.5 to
+
7.0V
−
1.5 to V
CC
+
1.5V
−
0.5 to V
CC
+
0.5V
±
20 mA
±
25 mA
±
50 mA
−
65
°
C to
+
150
°
C
−
40
+
85
°
C
Note 2:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 3:
Unless otherwise specified all voltages are referenced to ground.
Note 4:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
(Note 5)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
V
V
V
Units
Conditions
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
6.0V
V
IN
=
V
CC
or GND
4.5V
6.0V
6.0V
4.5V
6.0V
Note 5:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
www.fairchildsemi.com
MM74HC139
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation
Delay, Binary Select to any Output
4 levels of delay
t
PHL
, t
PLH
Maximum Propagation
Delay, Binary Select to any Output
5 levels of delay
t
PHL
, t
PLH
Maximum Propagation
Delay, Enable to any Output
19
30
ns
28
38
ns
Conditions
Typ
18
Guaranteed
Limit
30
Units
ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
(Note 6)
V
CC
2.0V
4.5V
6.0V
(Note 7)
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
C
IN
C
PD
Maximum Input
Capacitance
Power Dissipation
Capacitance (Note 8)
Note 6:
4 levels of delay are A to Y1, Y3 and B to Y2, Y3.
Note 7:
5 levels of delay are A to Y0, Y2 and B to Y0, Y1.
Note 8:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
T
A
=
25°C
Typ
110
22
18
165
33
28
115
23
19
30
8
7
3
175
35
30
220
44
38
175
35
30
75
15
13
10
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
219
44
38
275
55
47
219
44
38
95
19
16
10
254
51
44
320
64
54
254
51
44
110
22
19
10
Units
t
PHL
, t
PLH
Maximum Propagation
Delay Binary Select to
any Output 4 levels of delay
t
PHL
, t
PLH
Maximum Propagation
Delay Binary Select to any
Output 5 levels of delay
t
PHL
, t
PLH
Maximum Propagation
Delay Enable to any
Output
t
TLH
, t
TLH
Maximum Output Rise
and Fall Time
ns
ns
ns
ns
pF
pF
(Note 8)
75
www.fairchildsemi.com
4
MM74HC139
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
www.fairchildsemi.com
京公网安备 11010802033920号
EEWORLD
