a
FEATURES
140 MSPS Guaranteed Conversion Rate
100 MSPS Low Cost Version Available
330 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal +2.5 V Reference
Differential or Single-Ended Clock Input
3.3 V/5.0 V Three-State CMOS Outputs
Single or Demultiplexed Output Ports
Data Clock Output Provided
Low Power: 1.0 W Typical
+5 V Converter Power Supply
APPLICATIONS
RGB Graphics Processing
High Resolution Video
LCD Monitors and Projectors
Micromirror Projectors
Plasma Display Panels
Scan Converters
R AIN
R AIN
G AIN
G AIN
B AIN
B AIN
ENCODE
ENCODE
DS
DS
Triple 8-Bit, 140 MSPS
A/D Converter
AD9483
FUNCTIONAL BLOCK DIAGRAM
AD9483
T/H
QUANTIZER
8
D
R
A
7-0
D
R
B
7-0
T/H
QUANTIZER
8
D
G
A
7-0
D
G
B
7-0
T/H
QUANTIZER
8
D
B
A
7-0
D
B
B
7-0
TIMING
CLKOUT
CLKOUT
OMS
I/P
PD
CONTROL
+2.5V
VREF RVREF GVREF BVREF V
CC
V
DD
GND
OUT
IN
IN
IN
GENERAL DESCRIPTION
The AD9483 is a triple 8-bit monolithic analog-to-digital
converter optimized for digitizing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 330 MHz
supports display resolutions of up to 1280
×
1024 at 75 Hz with
sufficient input bandwidth to accurately acquire and digitize
each pixel.
To minimize system cost and power dissipation, the AD9483
includes an internal +2.5 V reference and track-and-hold cir-
cuit. The user provides only a +5 V power supply and an en-
code clock. No external reference or driver components are
required for many applications. The digital outputs are three-
state CMOS outputs. Separate output power supply pins sup-
port interfacing with 3.3 V or 5 V logic.
The AD9483’s encode input interfaces directly to TTL, CMOS,
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual channel or single
channel digital outputs. The Dual Channel (demultiplexed)
mode interleaves ADC data through two 8-bit channels at one-
half the clock rate. Operation in Dual Channel mode reduces
the speed and cost of external digital interfaces while allowing
the ADCs to be clocked to the full 140 MSPS conversion rate.
In the Single Channel mode, all data is piped at the full clock
rate to the Channel A outputs and the ADCs conversion rate is
limited to 100 MSPS. A data clock output is provided at the
Channel A output data rate for both Dual-Channel or Single-
Channel output modes.
Fabricated in an advanced BiCMOS process, the AD9483 is
provided in a space-saving 100-lead MQFP surface mount plas-
tic package (S-100) and is specified over the 0°C to +85°C
temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD9483–SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error
1
Gain Tempco
1
ANALOG INPUT
Input Voltage Range
(With Respect to
AIN)
Compliance Range AIN or
AIN
Input Offset Voltage
Input Resistance
Input Capacitance
Input Bias Current
Analog Bandwidth, Full Power
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (t
EH
)
Encode Pulsewidth Low (t
EL
)
Aperture Delay (t
A
)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
Data Sync Setup Time (t
SDS
)
Data Sync Hold Time (t
HDS
)
Data Sync Pulsewidth (t
PWDS
)
Output Valid Time (t
V
)
2
Output Propagation Delay (t
PD
)
2
Clock Valid Time (t
CV
)
3
Clock Propagation Delay (t
CPD
)
3
Data to Clock Skew (t
V
–t
CV
)
Data to Clock Skew (t
PD
–t
CPD
)
DIGITAL INPUTS
Input Capacitance
DIFFERENTIAL INPUTS
Differential Signal Amplitude (V
ID
)
HIGH Input Voltage (V
IHD
)
LOW Input Voltage (V
ILD
)
Common-Mode Input (V
ICM
)
HIGH Level Current (I
IH
)
LOW Level Current (I
IL
)
VREF IN
Input Resistance
+25°C
Full
+25°C
Full
Full
+25°C
Full
(V
CC
= +5 V, V
DD
= +3.3 V, external reference, ENCODE = maximum conversion rate
differential PECL)
Test
Level
AD9483KS-140
Min Typ
Max
8
I
VI
I
VI
VI
I
V
1.25/–1.0
1.50/–1.0
0.9
1.50/–1.50
1.75/–1.75
Guaranteed
±
1
±
2
160
0.8
AD9483KS-100
Min Typ Max
8
1.25/–1.0
1.50/–1.0
0.9
1.50/–1.50
1.75/–1.75
Guaranteed
±
1
±
2
160
0.8
Units
Bits
LSB
LSB
LSB
LSB
% FS
ppm/°C
Temperature
Full
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
+25°C
Full
Full
Full
Full
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
Full
Full
+25°C
Full
Full
Full
Full
Full
Full
+25°C
V
V
I
VI
I
VI
V
I
VI
V
VI
V
VI
IV
IV
IV
V
V
V
IV
IV
IV
VI
VI
VI
VI
VI
VI
V
IV
IV
IV
IV
VI
VI
V
±
512
1.8
±
4
83
4
17
330
+2.4 +2.5
110
140
2.8
2.8
1.5
100
2.3
0
0.5
2.0
4.0
3.8
–1.0
–2.0
0
0.5
2.0
4.0
10
3.8
10
1.0
2.0
–1.0
–2.0
10
50
50
+2.6
+2.4
3.2
±
16
±
20
1.8
±
512
±
4
83
4
17
330
+2.5
110
+2.6
3.2
±
16
±
20
35
25
35
25
36
50
36
50
mV p–p
V
mV
mV
kΩ
kΩ
pF
µA
µA
MHz
V
ppm/°C
MSPS
MSPS
ns
ns
ns
ps
ps rms
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
mV
V
V
V
mA
mA
kΩ
100
4.0
4.0
1.5
100
2.3
10
50
50
6.3
8.0
6.2
8.0
0
0
3
6.3
8.0
6.2
8.0
0
0
3
10
10
1.0
2.0
400
0.4
0
1.5
V
CC
1.2
1.2
2.5
400
0.4
0
1.5
V
CC
1.2
1.2
2.5
–2–
REV. A
AD9483
Parameter
SINGLE-ENDED INPUTS
HIGH Input Voltage (V
IH
)
LOW Input Voltage (V
IL
)
HIGH Level Current (I
IH
)
LOW Level Current (I
IL
)
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
POWER SUPPLY
V
CC
Supply Current
V
DD
Supply Current
Total Power Dissipation
4
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
5
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
IN
= 19.7 MHz
f
IN
= 49.7 MHz
f
IN
= 69.7 MHz
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
f
IN
= 19.7 MHz
f
IN
= 49.7 MHz
f
IN
= 69.7 MHz
Effective Number of Bits
f
IN
= 19.7 MHz
f
IN
= 49.7 MHz
f
IN
= 69.7 MHz
2nd Harmonic Distortion
f
IN
= 19.7 MHz
f
IN
= 49.7 MHz
f
IN
= 69.7 MHz
3rd Harmonic Distortion
f
IN
= 19.7 MHz
f
IN
= 49.7 MHz
f
IN
= 69.7 MHz
Crosstalk
Temperature
Full
Full
Full
Full
Full
Full
Test
Level
IV
IV
VI
VI
VI
VI
AD9483KS-140
Min
Typ
Max
2.0
0
V
CC
0.8
1
1
AD9483KS-100
Min
Typ
Max
2.0
0
V
CC
0.8
1
1
Units
V
V
mA
mA
V
V
V
DD
– 0.05
0.05
Binary
V
DD
– 0.05
0.05
Binary
215
60
1.3
20
100
215
60
1.3
20
100
Full
Full
Full
+25°C
+25°C
+25°C
+25°C
VI
VI
VI
V
V
V
V
1.0
4
20
1.5
1.5
1.0
4
20
1.5
1.5
mA
mA
W
mA
mW
ns
ns
+25°C
+25°C
+25°C
V
I
V
41
45
44
44
41
45
44
44
dB
dB
dB
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
V
I
V
V
I
V
V
I
V
V
I
V
V
40
44
43
42
7.0
6.8
6.8
63
58
51
56
54
51
55
40
44
43
42
7.0
6.8
6.8
63
58
51
56
54
51
55
dB
dB
dB
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dB
6.4
6.4
50
50
46
46
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2
t
V
and t
PDF
are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 5 pF.
3
t
CV
and t
CPD
are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 20 pF.
4
Measured under the following conditions: analog input is –1 dBFS at 19.7 MHz.
5
SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range.
Typical thermal impedance for the S-100 (MQFP) 100-lead package:
θ
JC
= 10°C/W,
θ
CA
= 17°C/W,
θ
JA
= 27°C/W.
Specifications subject to change without notice.
REV. A
–3–
AD9483
ABSOLUTE MAXIMUM RATINGS*
Table I. Output Coding
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
to 0.0 V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . V
CC
to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
Step
255
254
253
•
•
•
129
128
127
126
•
•
•
2
1
0
AIN–AIN
≥0.512
V
0.508 V
0.504 V
•
•
•
0.006 V
0.002 V
–0.002 V
–0.006 V
•
•
•
–0.504 V
–0.508 V
≤–0.512
V
Code
255
254
253
•
•
•
129
128
127
126
•
•
•
2
1
0
Binary
1111 1111
1111 1110
1111 1101
•
•
•
1000 0001
1000 0000
0111 1111
0111 1110
•
•
•
0000 0010
0000 0001
0000 0000
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% production tested.
II – 100% production tested at +25°C and sample tested at
specified temperatures.
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – 100% production tested at +25°C; guaranteed by design
and characterization testing.
ORDERING GUIDE
Model
AD9483KS-100
AD9483KS-140
AD9483/PCB
Temperature
Range
0°C to +85°C
0°C to +85°C
+25°C
Package
Description
Plastic Thin Quad Flatpack
Plastic Thin Quad Flatpack
Evaluation Board
Package
Option
S-100B
S-100B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9483 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD9483
PIN FUNCTION DESCRIPTIONS
Pin Number
1, 6, 7, 10, 20, 30, 40, 50,
60, 70, 73, 77, 78, 80, 81,
95, 96, 100
2
3
4
5
8
9
11, 21, 31, 41, 51, 61, 71
79, 82, 83, 93, 94, 98, 99
12–19
22–29
32–39
42–49
52–59
62–69
72
74
75
76
84
85
86
87
88
89
90
91
92
97
Name
Function
GND
ENCODE
ENCODE
DS
DS
DCO
DCO
V
DD
V
CC
D
B
B
7
–D
B
B
0
D
B
A
7
–D
B
A
0
D
G
B
7
–D
G
B
0
D
G
A
7
–D
G
A
0
D
R
B
7
–D
R
B
0
D
R
A
7
–D
R
A
0
NC
OMS
I/P
PD
R AIN
R AIN
R REF IN
G AIN
G AIN
G REF IN
B AIN
B AIN
B REF IN
REF OUT
Ground
Encode clock for ADC (ADC samples on rising edge of ENCODE).
Encode clock complement (ADC samples on falling edge of
ENCODE).
Data Sync Aligns output channels in Dual-Channel mode.
Data Sync complement.
Data Clock Output. Clock output at Channel A data rate.
Data Clock Output complement.
Output Power Supply. Nominally 3.3 V.
Converter Power Supply. Nominally 5.0 V.
Digital Outputs of Converter “B,” Channel B. D
B
B
7
is the MSB.
Digital Outputs of Converter “B,” Channel A. D
B
A
7
is the MSB.
Digital Outputs of Converter “G,” Channel B. D
G
B
7
is the MSB.
Digital Outputs of Converter “G,” Channel A. D
G
A
7
is the MSB.
Digital Outputs of Converter “R,” Channel B. D
R
B
7
is the MSB.
Digital Outputs of Converter “R,” Channel A. D
R
A
7
is the MSB.
No Connect.
Selects Single Channel or Dual Channel output mode, (HIGH = single,
LOW = demuxed).
Selects interleaved or parallel output mode, (HIGH = interleaved, LOW = parallel).
Power-Down and Three-State Select (HIGH = power-down).
Analog Input Complement for Converter “R.”
Analog Input True for Converter “R.”
Reference Input for Converter “R” (+2.5 V Typical,
±
10%).
Analog Input Complement for Converter “G.”
Analog Input True for Converter “G.”
Reference Input for Converter “G” (+2.5 V Typical,
±
10%).
Analog Input Complement for Converter “B.”
Analog Input True for Converter “B.”
Reference Input for Converter “B” (+2.5 V Typical,
±
10%).
Internal Reference Output (+2.5 V Typical); Bypass with 0.01
µF
to Ground.
REV. A
–5–
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