AT49BV3218-90TJ datasheet, PDF

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AT49BV3218-90TJ: DescriptionFlash, 2MX16, 90ns, PDSO48, 20 X12 MM, PLASTIC, MO-142DD, TSOP1-48; Categorystorage storage; File Size590KB，25 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT49BV3218-90TJ Overview

Flash, 2MX16, 90ns, PDSO48, 20 X12 MM, PLASTIC, MO-142DD, TSOP1-48

AT49BV3218-90TJ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	TSOP1
package instruction	20 X12 MM, PLASTIC, MO-142DD, TSOP1-48
Contacts	48
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	90 ns
Other features	TOP OR BOTTOM BOOT BLOCK
Spare memory width	8
startup block	BOTTOM
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	18.4 mm
memory density	33554432 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	48
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.65 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	12 mm

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Features

•

Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)

•

Access Time – 85 ns

•

Sector Erase Architecture

•

– Sixty-three 32K Word (64K Byte) Sectors with Individual Write Lockout

– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout

Fast Word Program Time – 15 µs

Fast Sector Erase Time – 200 ms

Dual-plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Eight 4K Word and Fifteen 32K Word Sectors

Memory Plane B: Forty-eight 32K Word Sectors

Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

Low-power Operation

– 25 mA Active

– 10 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

RESET Input for Device Initialization

Sector Lockdown Support

TSOP and CBGA Package Options

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

32-megabit

(2M x 16/4M x 8)

3-volt Only

Flash Memory

AT49BV3218

AT49BV3218T

AT49LV3218

AT49LV3218T

Not Recommended

for New Design

Use AT49BV/LV320(T)

or AT49BV/LV321(T)

Contact

Atmel to discuss

the latest design in trends

and options

Description

The AT49BV/LV3218(T) is a 2.65- to 3.3-volt (BV)/3.0V to 3.6V (LV) 32-megabit Flash

memory organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits

each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The

memory is divided into 71 sectors for erase operations. The device is offered in 48-

lead TSOP and 48-ball CBGA packages. The device has CE and OE control signals to

avoid any bus contention. This device can be read or reprogrammed using a single

2.65V power supply, making it ideally suited for in-system programming.

Pin Configurations

Pin Name

A0 - A20

RESET

RDY/BUSY

VPP

I/O0 - I/O14

I/O15 (A-1)

BYTE

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

READY/BUSY Output

Optional Power Supply

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

Rev. 2452F–FLASH–10/02

Device

Operation

READ:

The AT49BV/LV3218(T) is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

When the device is first powered on it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for

the command codes). The command sequences are written by applying a low pulse on the

WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the

falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of

CE or WE. Standard microprocessor write timings are used. The address locations used in the

command sequences are not affected by entering the command sequences.

RESET:

A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high-impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE:

Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE:

The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into 71 sec-

tors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a section is t

SEC

. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating in 2 µs.

BYTE/WORD PROGRAMMING:

Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t

cycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle.

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

SECTOR LOCKDOWN:

Each sector has a programming lockdown feature. This feature pre-

vents programming of data in the designated sectors once the feature has been enabled.

These sectors can contain secure code that is used to bring up the system. Enabling the lock-

down feature will allow the boot code to stay in the device while data in the rest of the device is

updated. This feature does not have to be activated; any sector’s usage as a write protected

region is optional to the user.

At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector,

the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked

down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION:

A software method is available to determine if program-

ming of a sector is locked down. When the device is in the software product identification

mode (see Software Product Identification Entry and Exit sections) a read from address loca-

tion 00002H within a sector will show if programming the sector is locked down. If the data on

I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown

feature has been enabled and the sector cannot be programmed. The software product identi-

fication exit code should be used to return to standard operation.

SECTOR LOCKDOWN OVERRIDE:

The only way to unlock a sector that is locked down is

through reset or power-up cycles. After power-up or reset, the content of a sector that is

locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME:

The Erase Suspend command allows the system to

interrupt a sector erase operation and then program or read data from a different sector within

the same plane. Since this device has a dual-plane architecture, there is no need to use the

Erase Suspend feature while erasing a sector when you want to read data from a sector in the

other plane. After the Erase Suspend command is given, the device requires a maximum time

of 15 µs to suspend the erase operation. After the erase operation has been suspended, the

plane that contains the suspended sector enters the erase-suspend-read mode. The system

can then read data or program data to any other sector within the device. An address is not

required during the Erase Suspend command. During a sector erase suspend, another sector

cannot be erased. To resume the sector erase operation, the system must write the Erase

Resume command. The Erase Resume command is a one-bus cycle command, which does

require the plane address (determined by A20 - A19). The device also supports an erase sus-

pend during a complete chip erase. While the chip erase is suspended, the user can read from

any sector within the memory that is protected. The command sequence for a chip erase sus-

pend and a sector erase suspend are the same.

PRODUCT IDENTIFICATION:

The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see “Operating Modes” on page 13 (for hardware operation) or “Software Product

Identification Entry/Exit” on page 20. The manufacturer and device codes are the same for

both modes.

128-BIT PROTECTION REGISTER:

The device contains a 128-bit register that can be used

for security purposes in system design. The protection register is divided into two 64-bit

blocks. The two blocks are designated as block A and block B. The data in block A is non-

changeable and is programmed at the factory with a unique number. The data in block B is

programmed by the user and can be locked out such that data in the block cannot be repro-

grammed. To program block B in the protection register, the four-bus cycle Program

Protection Register command must be used as shown in the Command Definition table on

page 7. To lock out block B, the four-bus cycle Lock Protection Register command must be

used as shown in the Command Definition table. Data bit D1 must be zero during the fourth

2452F–FLASH–10/02

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