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STRUCTURE
NAME OF PRODUCT
TYPE
FUNCTION
Silicon Monolithic Integrated Circuit
DC-AC Inverter Control IC
ＢＤ９８９３Ｆ
１．1ch control with Push-Pull
２．Lamp current and voltage sense feed back control
３．Sequencing easily achieved with Soft Start Control
４．Short circuit protection with Timer Latch
５．Under Voltage Lock Out
６．Short circuit protection with over voltage
７．Mode-selectable the operating or stand-by mode by stand-by pin
８．BURST mode controlled by PWM and DC input
○Absolute Maximum Ratings（Ta = 25℃）
Parameter
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Maximum Junction Temperature
*
Symbol
V
CC
Topr
Tstg
Pd
Tjmax
Limits
15
-35½+95
-55½+125
562
*
+150
Unit
V
℃
℃
mW
℃
Pd derated at 4.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Recommended operating condition
Parameter
Supply voltage
Drive output frequency
BCT oscillation frequency
Symbol
Vcc
f
OUT
f
BCT
Limits
4.5½14.0
20½150
0.10½0.50
Unit
V
KHz
KHz
Status of this document
The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If these are any uncertainty in translation version of this document, official version takes priority.
REV. A
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○Electric Characteristics（Ta=25℃，VCC=7V）
Parameter
（
（WHOLE DEVICE）
）
Operating current
Stand-by current
（
（OVER VOLTAGE DETECT）
）
FB over voltage detect
voltage
（
（STAND-BY CONTROL）
）
Stand-by voltage H1
（High
Active）
Stand-by voltage H2
（Low
Active）
Stand-by voltage L
（
（TIMER LATCH）
）
Timer Latch voltage
Timer Latch current
（
（OSC BLOCK）
）
Active edge Current
MAX DUTY
Soft start current
IS COMP detect Voltage
SS COMP detect voltage
SRT ON resistance
（
（UVLO BLOCK）
）
Operating voltage
Shut down voltage
（
（FEED BACK BLOCK）
）
IS threshold voltage
VS threshold voltage
IS source current 1
IS source current 2
VS source current
（
（Output BLOCK）
）
N1ch output voltage H
N2ch output voltage H
N1ch output voltage L
N2ch output voltage L
N1ch sink resistance
N1ch source resistance
N2ch sink resistance
N2ch source resistance
Drive output frequency
（
（BURST MODE）
）
BOSC Max voltage
BOSC Min Voltage
BOSC frequency
（
（COMP BLOCK）
）
Over voltage detect
Under voltage detect
Hysteresis width
Symbol
MIN.
I
CC
1
I
CC
2
Vovf
－
－
2.20
Limits
TYP.
8
2
2.40
Unit
MAX.
16
10
2.60
mA
μA
V
System ON
DUTY pin：0.5V→2.0V
BURST Dimming：100%→0%
System ON
DUTY pin：0.5V→2.0V
BURST Dimming：0%→100%
System OFF
Conditions
VstH1
2.3
－
VCC
V
VstH2
VstL
V
SCP
I
SCP
Iact
MAXDUTY
Iss
Visc
Vss
R
SRT
VuvloH
VuvloL
Vis
Vvs
Iis1
Iis2
Ivs
VoutN1H
VoutN2H
VoutN1L
VoutN2L
RsinkN1
RsourceN1
RsinkN2
RsourceN2
F
OUT
VburH
VburL
F
BOSC
V
COMP
H
V
COMP
L
⊿V
COMP
1.4
-0.3
1.9
0.5
1.25/RT
44
1.0
0.45
2.0
－
4.13
3.94
1.225
1.220
－
13.0
－
V
CC
-0.3
V
CC
-0.3
－
－
－
－
－
－
58.5
1.94
0.4
252.2
1.92
0.96
－
－
－
2.0
1.0
1.5/RT
46.4
2.0
0.50
2.2
200
4.30
4.10
1.250
1.250
－
20.0
－
V
CC
-0.1
V
CC
-0.1
0.1
0.1
4
7
4
7
60.0
2.0
0.5
260
2.00
1.00
0.1
2.1
0.8
2.1
1.5
1.75/RT
49
3.0
0.55
2.4
400
4.47
4.26
1.275
1.280
1.5
27.0
1.0
V
V
V
μA
A
%
μA
V
V
Ω
V
V
V
V
μA
μA
μA
V
V
V
V
Ω
Ω
Ω
Ω
kHz
V
V
Hz
V
V
V
f
OUT
=60kHz
DUTY=2.0V
DUTY=0V、IS=0.5V
－
0.3
0.3
8
14
8
14
61.5
2.06
0.6
267.8
2.08
1.04
0.15
Isink = 10mA
Isource = 10mA
Isink = 10mA
Isource = 10mA
RT=29.2kΩ
f
BCT
=0.2kHz
f
BCT
=0.2kHz
BCT=46420pF
（This product is not designed for normal operation with in a radio active environment.）
REV. A
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〇Package Dimensions
Device Mark
(include BURR : 10.35)
BD9893
F
Lot No.
SOP16 (unit:mm)
〇Block Diagram
SS
RT
BCT
DUTY
VCC
〇Pin Description
Pin
Name
RT
SRT
FB
IS
VS
GND
DUTY
BCT
COMP
SCP
SS
STB
N2
PGND
N1
VCC
Pin No.
+
OSC
STB
STB
BLOCK
BOSC
Function
External resistor from RT to GND for adjusting
the internal triangle oscillator
External resistor from SRT to RT for adjusting
the internal triangle oscillator
Error amplifier output
Error amplifier input①
Error amplifier input②
GROUND
Control PWM mode and BURST mode
External capacitor from BCT to GND for adjusting
the BURST triangle oscillator
Under, over voltage detect
External capacitor from SCP to GND for Timer
Latch
External capacitor from SS to GND for Soft Start
Control
Stand-by switch
Select the BURST dimming direction
FET driver
Ground for FET drivers
FET driver
Supply voltage input
-
1
2
SYSTEM ON/OFF
PWM
BLOCK
FB
3
LOGIC
BLOCK
OUTPUT
BLOCK
N1
N2
PGND
4
5
6
7
8
9
IS
-
+
1.25V
F/B
BLOCK
VCC
UVLO
VS
-
+
1.25V
-
+
VCC
REG
Reg
BLOCK
10
11
VS
IS
PROTECT
BLOCK
12
13
14
GND
COMP
SCP
SRT
15
16
REV. A
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〇
NOTE FOR USE
１． When designing the external circuit, including adequate margins for variation between external devices and the IC.Use
adequate margins for steady state and transient characteristics.
２． Recommended Operating Range
The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended
operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating
ranges, however the variation will be small.
３． Mounting failures, such as misdirection or miscounts, may harm the device.
４． A strong electromagnetic field may cause the IC to malfunction.
５.
The GND pin should be the location within
±0.3V compared with the PGND pin
６． The BD9893F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit)
is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee
its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation
of the thermal shutdown circuit is assumed.
７． Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened.
Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need
to be considered when using a device beyond its maximum ratings.
８． About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.
Make sure to leave adequate margin for this IC variation.
９． On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
１０． By STB voltage, BD9893F are changed to 3 states. Therefore, do not input STB pin voltage between one state and the other
state (0.8½1.4V, 2.1½2.3V).
１１．The pin connected a connector need to connect to the resistor for electrical surge destruction.
１２．This IC is a monolithic IC which (as shown is Fig-1)has P
+
substrate and between the various pins. A P-N junction is
formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which
parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin.
Resistance
(PinA)
(PinB)
C
Transistor (NPN)
B
E
GND
P
＋
P
N
P substrate
GND
Parasitic diode
N
P
＋
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B
Parasitic diode
GND
Ｃ
Ｎ
Ｎ
N
N
Ｂ
C
Ｃ
E
Ｅ
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A
Notice
Notes
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