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HI-5042, HI-5043, HI-5047, HI-5049, HI-5051
Data Sheet
April 6, 2005
FN3127.6
CMOS Analog Switches
This family of CMOS analog switches offers low resistance
switching performance for analog voltages up to the supply
rails and for signal currents up to 80mA. “ON” resistance is
low and stays reasonably constant over the full range of
operating signal voltage and current. r
ON
remains
exceptionally constant for input voltages between +5V and
-5V and currents up to 50mA. Switch impedance also
changes very little over temperature, particularly between
0
o
C and 75
o
C. r
ON
is nominally 25Ω for HI-5049 and
HI-5051 and 50Ω for HI-5042 through HI-5047.
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
very low input and output leakage currents (0.8nA at 25
o
C).
This family of switches also features very low power
operation (1.5mW at 25
o
C).
There are 7 devices in this switch series which are
differentiated by type of switch action and value of r
ON
(see
Functional Description Table). The HI-504X and HI-505X series
switches can directly replace IH-5040 series devices, and are
functionally compatible with the DG180 and DG190 family
Features
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . .
±15V
• Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 25Ω
• High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA
• Break-Before-Make Switching
- Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370ns
- Turn-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns
• No Latch-Up
• Input MOS Gates are Protected from Electrostatic
Discharge
• DTL, TTL, CMOS, PMOS Compatible
•
Pb-Free Available (RoHS Compliant)
Applications
• High Frequency Switching
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
S
A
N
P
D
Functional Description
PART NUMBER
HI-5042
HI-5043
HI-5047
HI-5049
HI-5051
SPDT
Dual SPDT
4PST
Dual DPST
Dual SPDT
TYPE
r
ON
50Ω
50Ω
50Ω
25Ω
25Ω
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-5042 thru HI-5051
Ordering Information
PART NUMBER
HI1-5042-2
HI1-5043-2
HI1-5043-5
HI3-5043-5
HI3-5043-5Z
(See Note)
HI9P5043-5
HI9P5043-5Z
(See Note)
HI1-5047-5
HI1-5049-5
HI1-5051-2
HI1-5051-5
HI3-5051-5
HI3-5051-5Z
(See Note)
HI9P5051-9
HI9P5051-9Z
(See Note)
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
-55 to 125
0 to 75
0 to 75
0 to 75
-40 to 85
-40 to 85
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP*
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP *
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
PKG.
DWG. #
F16.3
F16.3
F16.3
E16.3
F16.3
M16.15
M16.15
F16.3
F16.3
F16.3
F16.3
E16.3
E16.3
M16.15
M16.15
D
1
1
2
D
2
3
S
2
4
5
6
7
8
Pinouts
(SWITCHES SHOWN FOR LOGIC “0” INPUT)
Single Control
SPDT
HI-5042 (50Ω)
16 S
1
15 A
14 V-
13 V
R
12 V
L
11 V+
10
9
D
2
1
2
D
1
3
S
1
4
S
4
5
D
4
6
7
D
3
8
4PST
HI-5047 (50Ω)
16 S
2
15 A
14 V-
13 V
R
12 V
L
11 V+
10
9 S
3
NOTE: Unused pins may be internally connected. Ground all
unused pins.
Pinouts
(SWITCHES SHOWN FOR LOGIC “0” INPUT)
Dual Control
DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)
D
1
1
2
D
3
3
S
3
4
S
4
5
D
4
6
7
D
2
8
16 S
1
15 A
1
14 V-
13 V
R
12 V
L
11 V+
10 A
2
9 S
2
D
1
1
2
D
3
3
S
3
4
S
4
5
D
4
6
7
D
2
8
DUAL DPST
HI-5049 (25Ω)
16 S
1
15 A
1
14 V-
13 V
R
12 V
L
11 V+
10 A
2
9 S
2
*Pb-free
PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NOTE: Unused pins may be internally connected. Ground all
unused pins.
2
HI-5042 thru HI-5051
Switch Functions
(SWITCHES SHOWN FOR LOGIC “1” INPUT)
DUAL SPDT
HI-5043 (50Ω)
V
L
12
1
3
D
1
D
2
S
1
S
3
A
1
A
2
S
2
S
4
13
V
R
14
V-
16
4
15
10
9
5
13
V
R
14
V-
V+
11
1
3
D
1
D
3
SPDT
HI-5042 (50Ω)
V
L
12
S
1
S
2
16
4
V+
11
A
15
8
6
D
2
D
4
4PST
HI-5047 (50Ω)
V
L
12
S
1
S
2
S
3
S
4
A
4
16
9
5
15
V+
11
3
1
8
6
D
1
D
2
D
3
D
4
S
1
S
3
A
1
A
2
S
2
S
4
13
V
R
14
V-
16
4
15
10
9
5
DUAL DPST
HI-5049 (25Ω)
V
L
12
V+
11
1
3
D
1
D
3
S
1
S
3
A
1
8
6
13
V
R
14
V-
A
2
S
2
S
4
16
4
15
10
9
5
DUAL SPDT
HI-5051 (25Ω)
V
L
12
V+
11
1
3
D
1
D
3
D
2
D
4
8
6
13
V
R
14
V-
D
2
D
4
3
HI-5042 thru HI-5051
Schematic Diagrams
V+
V
L
35µA
R3
N13
100µA
25µA
25µA
QP1
25µA
P15
P14
R6
QP4
QN1
P16
QP3
R4
QP5
QP8
R2
QP7
V
R
QP6
P13
25µA
16µA
V+
R5
TO V
R
’
25µA
QP2
V-
N14
N15
N16
to V
L
’
N1
V+
IN
P2
V-
P1
N3
N2
OUT
R7
QN2
NOTE: Connect V+ to V
L
for minimizing power consumption when driving from CMOS circuits.
TTL/CMOS REFERENCE CIRCUIT
(NOTE)
A
1
(A
2
)
A
1
(A
2
)
SWITCH CELL
V+
P3
P5
P4
P6
V
R
'
D2
V
L
'
N6
V-
P2
N4
N2
N5
N3
V-
N7
N8
N9
N10
N11
N12
P7
P8
P9
P10
P11
P12
A1
A1
A2
A2
V+
P1
N1
D1
R4
A
200Ω
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
4
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