IS41C16100
IS41LV16100
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
— Auto refresh Mode:
1,024 cycles /16 ms
—
RAS-Only, CAS-before-RAS
(CBR), and Hidden
— Self refresh Mode
- 1,024 cycles / 128ms
• JEDEC standard pinout
• Single power supply:
— 5V ± 10% (IS41C16100)
— 3.3V ± 10% (IS41LV16100)
• Byte Write and Byte Read operation via two
CAS
• Industrail Temperature Range -40
o
C to 85
o
C
ISSI
April 2003
®
DESCRIPTION
The
ISSI
IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit
high-performance CMOS Dynamic Random Access Memories.
These devices offer an accelerated cycle access called EDO Page
Mode. EDO Page Mode allows 1,024 random accesses within a
single row with access cycle time as short as 20 ns per 16-bit word.
The Byte Write control, of upper and lower byte, makes the
IS41C16100 ideal for use in 16-bit and 32-bit wide data bus systems.
These features make the IS41C16100and IS41LV16100 ideally suited
for high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral applications.
The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-
mil SOJ and 400-mil 50- (44-) pin TSOP (Type II). The lead-free 400-
mil 50- (44-) option is available too.
KEY TIMING PARAMETERS
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
42-Pin SOJ
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
Min. EDO Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IIntegrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. I
04/16/03
1
IS41C16100
IS41LV16100
Functional Description
The IS41C16100 and IS41LV16100 is a CMOS DRAM
optimized for high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
ten bits (A0-A9) at time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS).
RAS
is used
to latch the first nine bits and
CAS
is used to latch the latter nine bits.
The IS41C16100 and IS41LV16100 has two
CAS
con-
trols,
LCAS
and
UCAS.
The
LCAS
and
UCAS
inputs internally
generates a
CAS
signal functioning in an identical manner to the
single
CAS
input on the other 1M x 16 DRAMs. The key differ-
ence is that each
CAS
controls its corresponding I/O
tristate logic (in conjunction with
OE
and
WE
and
RAS). LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8 through I/O15.
The IS41C16100 and IS41LV16100
CAS
function is
determined by the first
CAS
(LCAS or
UCAS)
transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16100 and IS41LV16100 both
BYTE READ and BYTE WRITE cycle capabilities.
ISSI
®
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully
static, low power data retention mode. The optional Self
Refresh feature is initiated by performing a CBR Refresh
cycle and holding
RAS
LOW for the specified t
RAS
.
The Self Refresh mode is terminated by driving
RAS
HIGH for a minimum time of t
RP
. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the
RAS
LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a
RAS-only
or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the
resumption of normal operation.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through A9)
with
RAS
at least once every 128 ms. Any read, write, read-
modify-write or
RAS-only
cycle refreshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. I
04/16/03
Analogue and Mixed Signal
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