BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
256K X 16 bit
DESCRIPTION
BS616LV4010
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V
C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
-10
100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV4010 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV4010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4010 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-pin BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV4010DC
BS616LV4010EC
BS616LV4010AC
BS616LV4010BC
BS616LV4010DI
BS616LV4010EI
BS616LV4010AI
BS616LV4010BI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
Vcc=3.0V
( I
CCSB1
, Max )
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
PKG TYPE
DICE
TSOP2-44
BGA-48-0608
BGA-48-0810
DICE
TSOP2-44
BGA-48-0608
BGA-48-0810
Vcc=3.0V
Vcc=3.0V
+0 C to +70 C
O
O
2.7V ~ 3.6V
70 / 100
8uA
20mA
-40
O
C to +85
O
C
2.7V ~ 3.6V
70 / 100
12uA
25mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
BLOCK DIAGRAM
BS616LV4010EC
BS616LV4010EI
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 2048
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS616LV4010
1
Revision 2.4
Jan.
2004
BSI
PIN DESCRIPTIONS
BS616LV4010
Name
A0-A17 Address Input
CE Chip Enable Input
Function
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active to read from or write to the device. if
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
Vcc
Gnd
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
CE
H
L
L
WE
X
H
H
OE
X
H
L
LB
X
X
L
H
L
L
Write
L
L
X
H
L
UB
X
X
L
L
H
L
L
H
DQ0~DQ7
High Z
High Z
Dout
High Z
Dout
Din
X
Din
DQ8~DQ15
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
R0201-BS616LV4010
2
Revision 2.4
Jan.
2004
BSI
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
BS616LV4010
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +125
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
2.7V ~ 3.6V
2.7V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
, or OE = V
IH
,
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE = V
IL
, I
DQ
= 0mA, F = Fmax
(3)
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
TEST CONDITIONS
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
MIN. TYP.
-0.5
2.0
--
--
--
2.4
--
--
--
--
--
--
--
--
(1 )
MAX.
0.8
Vcc+0.2
1
1
0.4
--
20
UNITS
V
V
uA
uA
V
V
mA
I
CCSB
CE = V
IH
, I
DQ
= 0mA
CE
≧
Vcc-0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
Vcc=3.0V
--
--
1
mA
I
CCSB1
Standby Current-CMOS
Vcc=3.0V
--
0.5
8
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
TEST CONDITIONS
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN. TYP.
1.5
--
0
T
RC (2)
--
(1)
MAX.
--
1
--
--
UNITS
V
uA
ns
ns
0.3
--
--
1. Vcc = 1.5V, T
A
= + 25 C
2. t
RC
= Read Cycle Time
R0201-BS616LV4010
3
Revision 2.4
Jan.
2004
BSI
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
Data Retention Mode
BS616LV4010
V
DR
≥
1.5V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
1V/ns
0.5Vcc
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
1269
Ω
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
1269
Ω
3.3V
OUTPUT
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
5PF
1404
Ω
INCLUDING
JIG AND
SCOPE
,
1404
Ω
FIGURE 1A
THEVENIN EQUIVALENT
667
Ω
FIGURE 1B
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
←
→
←
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 70ns
MIN. TYP. MAX.
CYCLE TIME : 100ns
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
70
--
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
--
--
35
35
30
--
100
--
--
--
--
15
15
15
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
--
--
40
40
35
--
NOTE :
1. t
BA
is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; t
BA
is 70ns/100ns (@speed=70ns/100ns) without address toggle.
R0201-BS616LV4010
4
Revision 2.4
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616LV4010
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE
t
ACS
t
BA
LB,UB
t
BE
D
OUT
t
(5)
CLZ
t
BDO
t
(5)
CHZ
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
OE
AA
t
OE
CE
t
OH
t
OLZ
t
(5)
CLZ
t
ACS
t
OHZ
(5)
(1,5)
t
CHZ
t
BA
LB,UB
t
BE
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
t
BDO
5. Transition is measured
±
500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616LV4010
Revision 2.4
Jan.
2004
5
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