BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Dual CE Pins)
DESCRIPTION
BS616LV8013
• Vcc operation voltage :
2.7~3.6V
• Very low power consumption :
Vcc =
3.0V
C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.)
CMOS standby current
• High speed access time :
-55
-70
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV8013 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a range of
2.7V to 3.6V
supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of
1.5uA
at
3V/25
o
C
and maximum access time of 55ns at
3V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616LV8013 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8013 is available in 48-pin BGA package.
PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
+0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
RANGE
2.7V ~ 3.6V
2.7V ~ 3.6V
SPEED
(ns)
55ns : 3.0~3.6V
70ns : 2.7~3.6V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=3V
Vcc=3V
55ns
Vcc=3V
70ns
BS616LV8013FC
BS616LV8013FI
55 / 70
55 / 70
5 uA
10uA
30mA
31mA
24mA
25mA
BGA-48-0912
BGA-48-0912
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
2
OE
UB
D10
D11
3
A0
A3
A5
A17
VSS
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
WE
A11
6
CE2
D0
D2
VCC
VSS
D6
D7
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
4096
D0
16
Data
Input
Buffer
16
Column I/O
VCC
D14
D15
A 18
D12
D13
NC
.
A8
.
.
.
.
D15
CE2
CE1
WE
OE
UB
LB
.
.
.
.
Write Driver
Sense Amp
256
Column Decoder
16
Data
Output
16
Buffer
16
Control
Address Input Buffer
NC
A11 A10 A9 A8 A7 A6 A5 A18
Vcc
Vss
48-Ball CSP top View
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
R0201-BS616LV8013
1
Revision 1.1
Jan.
2004
BSI
PIN DESCRIPTIONS
BS616LV8013
Function
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
Name
A0-A18 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Vss
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
CE1
H
X
L
L
CE2
X
L
H
H
WE
X
X
H
H
OE
X
X
H
L
LB
X
X
X
L
H
L
L
Write
L
H
L
X
H
L
UB
X
X
X
L
L
H
L
L
H
D0~D7
High Z
High Z
High Z
Dout
High Z
Dout
Din
X
Din
D8~D15
High Z
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
OPERATING RANGE
UNITS
V
O
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
2.7V ~ 3.6V
2.7V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
C
IN
V
IN
=0V
10
pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
C
DQ
V
I/O
=0V
12
pF
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
1. This parameter is guaranteed and not 100% tested.
maximum rating conditions for extended periods may affect reliability.
R0201-BS616LV8013
2
Revision 1.1
Jan.
2004
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(4)
BS616LV8013
TEST CONDITIONS
Vcc=3V
Vcc=3V
PARAMETER
Guaranteed Input Low
Voltage
(3)
Guaranteed Input High
Voltage
(3)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
MIN. TYP.
-0.5
--
(1)
MAX.
0.8
Vcc+0.3
1
1
0.4
--
31
25
1
UNITS
V
V
uA
uA
V
V
mA
mA
2.0
--
--
--
2.4
--
--
--
--
--
--
--
--
--
--
--
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE1 = V
IH
, or CE2 =
V
iL
, or
OE = V
IH
, V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE1 = V
IL
and CE2 = V
IH
, I
DQ
= 0mA, F = Fmax
(2)
CE1 = V
IH
or CE2 = V
IL
, I
DQ
= 0mA
CE1
≧
Vcc-0.2V or
CE2
≦
0.2V ;V
IN
≧
Vcc - 0.2V
or V
IN
≦
0.2V
55ns
70ns
Vcc=3V
Vcc=3V
Vcc=3V
I
CCSB
Vcc=3V
I
CCSB1
(5)
Standby Current-CMOS
Vcc=3V
--
1.5
10
uA
1. Typical characteristics are at TA = 25
o
C.
2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc
_Max.
is
30mA(@55ns)
/
24mA(@70ns)
during 0~70
o
C operation.
5.I
cc
s
B1
is
5uA
at Vcc=3.0V and T
A
=70
o
C.
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
V
DR
(3)
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN. TYP.
1.5
--
0
T
RC (2)
--
(1)
MAX.
--
2.5
--
--
UNITS
V
uA
ns
ns
I
CCDR
t
CDR
t
R
0.8
--
--
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
O
C.
3. I
cc
DR
(Max.) is
1.3uA
at T
A
=70
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
≥
1.5V
Vcc
t
CDR
CE1
≥
Vcc - 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
V
DR
≧
1.5V
Vcc
t
CDR
t
R
CE2
≦
0.2V
CE2
R0201-BS616LV8013
V
IL
V
IL
3
Revision 1.1
Jan.
2004
BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
BS616LV8013
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
(CE2,CE1)
(LB,UB)
(CE1)
(CE2)
(LB,UB)
CYCLE TIME : 70ns CYCLE TIME : 55ns
MIN. TYP. MAX.
Vcc = 2.7~3.6V
Vcc = 3.0~3.6V
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
ELQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS1
t
ACS2
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
70
--
--
--
--
--
10
5
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
35
--
--
--
35
35
30
--
55
--
--
--
--
--
10
5
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
30
30
--
--
--
30
30
25
--
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z (CE2,CE1)
Data Byte Control to Output High Z (LB,UB)
Output Disable to Output in High Z
Data Hold from Address Change
NOTE :
1. t
BA
is 35ns/30ns (@speed=70ns/55ns) with address toggle .
t
BA
is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV8013
4
Revision 1.1
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616LV8013
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE2
t
t
ACS2
ACS1
CE1
t
D
OUT
(5)
CLZ
(5)
t
CHZ
READ CYCLE3
(1,4)
ADDRESS
t
RC
t
OE
AA
t
CE2
OE
t
OH
t
t
t
t
(5)
CLZ
ACS2
CE1
OLZ
ACS1
t
t
OHZ
CHZ
(5)
(1,5)
LB,UB
t
BE
t
t
BA
BDO
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2 = V
IH.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
R0201-BS616LV8013
5
Revision 1.1
Jan.
2004
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