HY5V56D(L/S)FP Series
4 Banks x 4M x 16bits Synchronous DRAM
DESCRIPTION
The HY5V56D(L/S)FP is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which
require low power consumption and industrial temperature range. HY5V56D(L/S)FP is organized as 4banks of
4,194,304x16
HY5V56D(L/S)FP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
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•
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Single 3.3±0.3V power supply
All device balls are compatible with LVTTL interface
54Ball FBGA (13.5mm x 8.0mm)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
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Internal four banks operation
Programmable CAS Latency ; 2, 3 Clocks
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Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY5V56DFP-H
HY5V56DFP-8
HY5V56DFP-P
HY5V56DFP-S
HY5V56D(L/S)FP-H
HY5V56D(L/S)FP-8
HY5V56D(L/S)FP-P
HY5V56D(L/S)FP-S
Clock Frequency
133MHz
125MHz
100MHz
100MHz
133MHz
125MHz
100MHz
100MHz
Low
power
Normal
54ball FBGA
/
Lead free
Power
Organization
Interface
Package
4Banks x 4Mbits x16
LVTTL
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / Jan. 2005
2
HY5V56D(L/S)FP
BALL DESCRIPTION
BALL OUT
F2
SYMBOL
CLK
TYPE
INPUT
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend or self
refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and
LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
F3
CKE
INPUT
G9
CS
INPUT
G7,G8
H7, H8, J8, J7, J3,
J2, H3, H2, H1,
G3, H9, G2,
G1
F8, F7, F9
BA0, BA1
INPUT
A0 ~ A12
INPUT
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS,
WE
UDQM,
LDQM
INPUT
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:Controls output buffers in read mode and masks input data
in write mode
F1, E8
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
A9, E7, J9, A1,
E3, J1
A7, B3, C7, D3,
A3, B7, C3, D7
E2, G1
INPUT
DQ0 ~ DQ15
I/O
Data Input/Output:Multiplexed data input/output ball
VDD/VSS
SUPPLY
Power supply for internal circuits
VDDQ/VSSQ
NC
SUPPLY
-
Power supply for output buffers
No connection
Rev. 0.1 / Jan. 2005
4
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