HYB3117400BTL-50 datasheet, PDF

HYB3117400BTL-50: DescriptionFast Page DRAM, 4MX4, 50ns, CMOS, PDSO40; Categorystorage storage; File Size736KB，26 Pages; ManufacturerSIEMENS; Websitehttp://www.infineon.com/

Download Datasheet Parametric Compare View All

HYB3117400BTL-50 Overview

Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO40

Parameter Name	Attribute value
Maker	SIEMENS
package instruction	,
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FAST PAGE
Maximum access time	50 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
JESD-30 code	R-PDSO-G40
memory density	16777216 bit
Memory IC Type	FAST PAGE DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	40
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
refresh cycle	2048
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal location	DUAL

	HYB3117400BTL-50	HYB3117400BTL-60
Description	Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO40	Fast Page DRAM, 4MX4, 60ns, CMOS, PDSO40
Maker	SIEMENS	SIEMENS
Reach Compliance Code	unknown	unknown
ECCN code	EAR99	EAR99
access mode	FAST PAGE	FAST PAGE
Maximum access time	50 ns	60 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
JESD-30 code	R-PDSO-G40	R-PDSO-G40
memory density	16777216 bit	16777216 bit
Memory IC Type	FAST PAGE DRAM	FAST PAGE DRAM
memory width	4	4
Number of functions	1	1
Number of ports	1	1
Number of terminals	40	40
word count	4194304 words	4194304 words
character code	4000000	4000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C
organize	4MX4	4MX4
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified
refresh cycle	2048	2048
self refresh	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal location	DUAL	DUAL

PWM continuous delay output problem: Last weekend, my boss asked me to do a task: a PWM signal, which required to be outputted as is after a delay of 0.5-5s.The signal that arrives first will be stored first, and then output after a dela...; fengkb MCU

Research on low-power wireless Internet of Things wake-up method: [color=#343434][font=宋体][size=4] [/size][/font][/color][font=宋体][size=6][color=#343434]Research on wake-up method of low-power wireless Internet of Things[/color][/size][/font][color=#343434][font=宋体]...; lclhitwh Wireless Connectivity

HWREG() assignment problem in LM3S8962 driver library: Today I encountered a problem when accessing memory with HWEG() HWREG (0x20000000) = 0xAA55AA55; No problem But given HWREG (0x20000000) = 0xAA55AA00; the program just keeps executing as if it is stuc...; new_redstar Microcontroller MCU

Solution to the conflict between MDK and C51 in the same computer: You can install RealView MDK and C51 on different disks and open them using different shortcuts....; 小野狼 Embedded System

Newbie question, thanks for the help!: I got the qy-9315 industrial control board, which is: wince5.0, which contains sdk, kernel image, etc. I don't know how to build the whole platform, that is: simulate running on this pc and debug winc...; phonesu Embedded System

EE_FPGA Basic Tutorial Series-- NO.4--Key Debounce: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! The original code was wrong. Thanks to the 6th and 7th floor for their careful interpretation. The overall program part in the article has been corrected. Apolo...; chenzhufly FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components