Preliminary
HY5V26D(L)F(P) Series
4Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V26D(L)F(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory appli-
cations which require wide data I/O and high bandwidth. HY5V26D(L)F(P) is organized as 4banks of 2,097,152x16.
HY5V26D(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
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Voltage : VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
Package Type : 54Ball FBGA (Lead or Lead Free)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
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Internal four banks operation
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Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
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Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / Jan. 2004
2
Preliminary
HY5V26D(L)F(P) Series
4Banks x 2M x 16bits Synchronous DRAM
Ball FUNCTION DESCRIPTIONS
Ball Out
F2
F3
G9
G7,G8
H7, H8, J8,
J7, J3, J2,
H3, H2, H1,
G3, H9, G2
F8, F7, F9
F1, E8
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1,
A2
A9, E7, J9,
A1, E3, J1
A7, B3, C7,
D3, A3, B7,
C3, D7
E2, G1
SYMBOL
CLK
CKE
CS
BA0, BA1
TYPE
INPUT
INPUT
INPUT
INPUT
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend or self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:Controls output buffers in read mode and masks input data in
write mode
A0 ~ A11
INPUT
RAS, CAS,
WE
UDQM,
LDQM
INPUT
INPUT
DQ0 ~
DQ15
I/O
Data Input/Output:Multiplexed data input/output pin
VDD/VSS
SUPPLY
Power supply for internal circuits
VDDQ/VSSQ
NC
SUPPLY
-
Power supply for output buffers
No connection : These pads should be left unconnected
Rev. 0.1 / Jan. 2004
5
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