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HD151011
Function Table
Control Inputs
CLR
H
X
—
—
L
H
Note:
PR
H
X
—
—
H
L
1.
2.
3.
4.
SPE
H
L
—
—
—
—
C/T
X
X
H
L
—
—
Mode
Generally count
Synchronous preset
—
—
Initialize of Q output
Initialize of Q output
Operation Description
Down count at the rise edge of clock (CLK)
Down count at the fall edge of clock (CLK)
Jn data is preset at the rise of clock (CLK), the
fall of clock (CLK)
Clock inputs (CLK,
CLK)
is CMOS level
Clock inputs (CLK,
CLK)
is TTL level
Initialize of Q = “L”
Initialize of Q = “H”
H
L
X
—
:
:
:
:
Synchronous preset (SPE) input can set max 99 down counts.
When the count value is 0, the next clock pulse presets the data to invert the output.
CLR and PR inputs initialize output state.
Clock inputs (CLK,
CLK)
is selectable CMOS level (V
CC
= 2.0 to 6.0 V) and TTL level (V
CC
= 4.5
to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level)
Don't set data exceeding 99 to Jn. (J0 : LSB, J7 : MSB)
High level
Low level
Immaterial
Irrespective of condition
2
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