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IDT7024L25FGB

Description
Dual-Port SRAM, 4KX16, 25ns, CMOS, 1.170 X 1.170 INCH, 0.110 INCH HEIGHT, GREEN, QFP-84
Categorystorage    storage   
File Size181KB,22 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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IDT7024L25FGB Overview

Dual-Port SRAM, 4KX16, 25ns, CMOS, 1.170 X 1.170 INCH, 0.110 INCH HEIGHT, GREEN, QFP-84

IDT7024L25FGB Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionQFF, QFL84,1.2SQ
Contacts84
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time25 ns
I/O typeCOMMON
JESD-30 codeS-XQFP-F84
JESD-609 codee3
length29.21 mm
memory density65536 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Number of functions1
Number of ports2
Number of terminals84
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize4KX16
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeQFF
Encapsulate equivalent codeQFL84,1.2SQ
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class B
Maximum seat height3.556 mm
Maximum standby current0.004 A
Minimum standby current2 V
Maximum slew rate0.28 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceMATTE TIN
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width29.21 mm
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
Features
IDT7024S/L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts availble, see ordering information
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
A
11L
A
0L
(1,2)
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
Address
Decoder
12
(1,2)
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
CE
L
OE
L
R/W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(2)
2740 drw 01
M/S
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC 2740/13
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