PRELIMINARY
PDM31048LL
256K x 8-Bit Low Power
3.3 Volt
Features
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Description
The PDM31048LL is a very low power CMOS static
RAM organized as 131,072 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE1) inputs are both LOW, and
CE2 is high. Reading is accomplished when WE and
CE2 remain HIGH and CE1 and OE are both LOW.
The PDM31048LL operates from a single +3.3V
power supply and all the inputs and outputs are
fully TTL- compatible. The device supports low data
retention voltage for battery back-up operation with
low current.
The PDM31048LL is available in a 32-pin plastic
TSOP (I) and a 32-pin plastic STSOP (I).
High-speed access times
Com’l: 70, 85 and 100ns
Low power operation (typical)
- PDM31048LL
Active: 65 mW
Standby: 7µW
Single +3.3V (±0.3V) power supply
TTL-compatible inputs and outputs
I/Os are 5V tolerant
Low data retention voltage: 1.5V
Packages
Plastic TSOP (I) - T
Plastic STSOP (I) - ST
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Functional Block Diagram
Addresses
A
0
•
•
•
•
•
A
17
Decoder
•
•
•
•
•
•
Memory
Matrix
I/O
0
•
•
I/O
7
• • • • •
Input
Data
Control
Column I/O
•
•
CE1
CE2
WE
OE
•
Control
Rev. 0.0 - 4/03/98
1
PRELIMINARY
PDM31048LL
Pin Configurations
TSOP (I), STSOP (I)
Pin Description
Name
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Inputs
Power (+3.3V)
Ground
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
A3
A17-A0
I/O7-I/O0
OE
WE
CE1, CE2
V
CC
V
SS
Truth Table
OE
X
X
L
X
H
WE
X
X
H
L
H
CE1
H
X
L
L
L
CE2
X
L
H
H
H
I/O
Hi-Z
Hi-Z
D
OUT
D
IN
Hi-Z
MODE
Standby
Standby
Read
Write
Output Disable
NOTE: H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
T
j
Rating
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature
(2)
Com’l.
–0.5 to +4.6
–55 to +125
–55 to +125
1.0
20
125
Ind.
–0.5 to +4.6
–65 to +135
–65 to +150
1.0
20
125
Unit
V
°C
°C
W
mA
°C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
θ
ja
the thermal resistance of the package. For
this product, use the following
θ
ja
values:
SOJ: 78
o
C/W
TSOP: 112
o
C/W
2
Rev. 0.0 - 4/03/98
PRELIMINARY
PDM31048LL
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Min.
3.0
0
0
Typ.
3.3
0
25
Max.
3.6
0
70
Unit
V
V
°C
DC Electrical Characteristics
(V
CC
= 3.3V
±
0.3V)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Conditions
V
CC
= MAX., V
IN
= Vss to V
CC
V
CC
= MAX.,
CE1= V
IH
, or
CE2 = V
IL
V
OUT
= Vss to
V
CC
Min.
–1
–1
Typ.
(2)
—
—
Max.
1
1
Unit
µA
µA
V
IL
V
IH
V
OL
V
OH
I
CC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
I
OL
= 2mA, V
CC
= Min.
I
OH
= –1 mA,
V
CC
= Min.
V
CC
= MAX
CE1 = V
IL,
CE2 =V
IH
I
OUT
= 0 mA
f = f
MAX
V
CC
= MAX
CE1 = V
IH
or
CE2
=
V
IL
V
CC
= MAX
CE1
≥
V
CC
-0.2V,
CE2
≤
0.2V
V
IN
≥
V
CC
-0.2V
or
≤
0.2V
–0.3
(1)
2.2
—
2.4
—
—
—
—
—
—
0.8
Vcc+0.3
0.4
—
40
V
V
V
V
mA
I
SB
Standby Current (TTL)
—
—
1
mA
I
SB1
Full Standby Current
(CMOS)
—
2
µA
40
µA
NOTE:1.V
IL
(min) = –3.0V for pulse width less than 20 ns. 2. V
CC
= 3.3V, 25C.
Rev. 0.0 - 4/03/98
3
PRELIMINARY
PDM31048LL
Data Retention Characteristics
Symbol
V
DR
Parameter
V
CC
for data retention
Test Conditions
CE1
≥
V
CC
-0.2V
CE2
≤
0.2V
V
IN
≥
V
CC
-0.2V
or
≤
0.2V
CE1
≥
V
CC
-0.2V
CE2
≤
0.2V
V
IN
≥
V
CC
-0.2V
or
≤
0.2V
See waveform
See waveform
Min.
1.5
Typ.
(1)
—
Max.
—
Unit
V
I
CC DR
Data retention current
—
1
20
µA
t
CDR
t
R
Chip deselect to data
retention time
Recovery time
0
t
RC
—
—
—
—
ns
ns
NOTE: 1. V
CC
= 3.3V, 25C.
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
6
8
Unit
pF
pF
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
5 ns
1.5V
1.5V
See Figures 1 and 2
4
Rev. 0.0 - 4/03/98
PRELIMINARY
PDM31048LL
+3.3V
+3.3V
319Ω
DATA
OUT
353Ω
100 pF
319Ω
DATA
OUT
353Ω
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
Low V
CC
Data Retention Waveform
Data Retention Mode
V CC
3.3V
VDR
3.3V
t
CDR
VIH
IL
VDR
t
RC
CE1
V
VIH
CE2
V IL
DON'T CARE
≤
0.2V
Rev. 0.0 - 4/03/98
5
Integrated technical exchanges
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