IDT707278S15PF9 datasheet, PDF

Datasheet> All Categories > storage> storage> IDT707278S15PF9

IDT707278S15PF9: DescriptionDual-Port SRAM, 32KX16, 15ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100; Categorystorage storage; File Size125KB，16 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric Compare View All

IDT707278S15PF9 Overview

Dual-Port SRAM, 32KX16, 15ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT707278S15PF9 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	QFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	15 ns
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
memory density	524288 bit
Memory IC Type	DUAL-PORT SRAM
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX16
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

Preview

Download Datasheet

View All

HIGH-SPEED

32K x 16 BANK-SWITCHABLE

DUAL-PORTED SRAM WITH

EXTERNAL BANK SELECTS

Features

◆

IDT707278S/L

◆

Functional Block Diagram

R/W

D S

N N

E G

M SI

M E

O D

E W

R E

T N

MUX

CONTROL

LOGIC

8Kx16

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

8L-15L

I/O

0L-7L

I/O

CONTROL

MUX

I/O

CONTROL

12L

0L(1)

ADDRESS

DECODE

8Kx16

MEMORY

ARRAY

(BANK 1)

MUX

ADDRESS

DECODE

BANK

DECODE

BANK

DECODE

MUX

8Kx16

MEMORY

ARRAY

(BANK 3)

MUX

BKSEL

3(2)

BKSEL

0(2)

BANK

SELECT

5L(1)

0L(1)

/UB

R/W

MAILBOX

INTERRUPT

LOGIC

5R(1)

0R(1)

/UB

R/W

MBSEL

INT

32K x 16 Bank-Switchable Dual-Ported SRAM Architecture

– Four independent 8K x 16 banks

– 512 Kilobit of memory on chip

Fast asynchronous address-to-data access time: 15ns

User-controlled input pins included for bank selects

Independent port controls with asynchronous address &

data busses

Four 16-bit mailboxes available to each port for inter-

processor communications; interrupt option

◆

Interrupt flags with programmable masking

Dual Chip Enables allow for depth expansion without

external logic

and

are available for x8 or x16 bus matching

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)

R/W

I/O

8R-15R

I/O

0R-7R

12R

0R(1)

MBSEL

INT

3739 drw 01

NOTES:

1. The first six address pins for each port serve dual functions. When

MBSEL

= V

, the pins serve as memory address inputs. When

MBSEL

= V

, the pins

serve as mailbox address inputs.

2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for

more details.

MAY 2000

DSC 3739/6

IDT707278S15PF9 Related Products

	IDT707278S15PF9	IDT707278L25PF9	IDT707278S20PF9	IDT707278S25PF9	IDT707278L20PF9	IDT707278L15PF9
Description	Dual-Port SRAM, 32KX16, 15ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 32KX16, 25ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 32KX16, 20ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 32KX16, 25ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 32KX16, 20ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	Dual-Port SRAM, 32KX16, 15ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	QFP,	QFP,	QFP,	QFP,	QFP,	QFP,
Contacts	100	100	100	100	100	100
Reach Compliance Code	compliant	compliant	compliant	compliant	unknown	compliant
ECCN code	3A991.B.2.B	EAR99	3A991.B.2.B	EAR99	3A991.B.2.B	3A991.B.2.B
Maximum access time	15 ns	25 ns	20 ns	25 ns	20 ns	15 ns
JESD-30 code	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100
JESD-609 code	e0	e0	e0	e0	e0	e0
length	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
memory density	524288 bit	524288 bit	524288 bit	524288 bit	524288 bit	524288 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1
Number of terminals	100	100	100	100	100	100
word count	32768 words	32768 words	32768 words	32768 words	32768 words	32768 words
character code	32000	32000	32000	32000	32000	32000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	32KX16	32KX16	32KX16	32KX16	32KX16	32KX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QFP	QFP	QFP	QFP	QFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	-	incompatible
Humidity sensitivity level	3	3	3	3	-	3
Peak Reflow Temperature (Celsius)	240	240	240	240	-	240
Maximum time at peak reflow temperature	20	20	20	20	-	20

Recommended Resources

Infrared remote control transmitter circuit

Shuttle loom motor contactless switch control circuit_1

Human body sensor alarm

Single pulse generation circuit diagram

555 negative voltage source circuit

Internal structure of ATCl05

Can you guys help me figure out what electronic component this is?: I can't find this model number online? Does anyone know what model it is and what electronic components it contains?...; 小太阳yy Analog electronics

MSP430 ADC acquisition filter: Placeholder 1 /* Weighted average filter */2static unsigned char coe[13] = {1,2,3,4,5,6,7,8,9,10,11,12,13};3static unsigned int coeSum= 1+2+3+4+5+6+7+8+9+10+11+12+13;4unsigned long temp = 0;56for (i =...; fish001 Microcontroller MCU

Testbench: //testbench for vgasdram `timescale 1ns/1ns module tb_m4kram; reg clk; //system clock, 50MHz reg rst_n; //reset signal, low level valid reg wren; //RAM write enable signal, high means write reg[11:0] ...; 火箭_1991 FPGA/CPLD

Zigbee wireless transparent transmission has achieved one-to-one, point-to-multipoint? ? ? Please guide me: ~~Waiting online~~ Please give me some advice!!!...; anday RF/Wirelessly

Basic requirements for wiring in high-speed PCB design: Conventional PCB routing in high-speed PCB design has the following basic requirements: (1) The rectangular pad lead of QFP, SOP and other packages should be led out from the center of the PIN (genera...; 高速PCB设计 Integrated technical exchanges

Share the revised FPGA development board design, welcome everyone to criticize: The full text continues from the last time. Three months after I helped the teacher draw an experimental board, the test has passed and the effect is pretty good, but the board lacks a human-machine i...; fsyicheng FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components