IDT707278S15PF datasheet, PDF - EEWORLD Datasheet

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IDT707278S15PF: DescriptionDual-Port SRAM, 32KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100; Categorystorage storage; File Size133KB，16 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT707278S15PF Overview

Dual-Port SRAM, 32KX16, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT707278S15PF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.B
Maximum access time	15 ns
I/O type	COMMON
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
memory density	524288 bit
Memory IC Type	DUAL-PORT SRAM
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	100
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.015 A
Minimum standby current	4.5 V
Maximum slew rate	0.35 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

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HIGH-SPEED

32K x 16 BANK-SWITCHABLE

DUAL-PORTED SRAM WITH

EXTERNAL BANK SELECTS

IDT707278S/L

Features

32K x 16 Bank-Switchable Dual-Ported SRAM Architecture

– Four independent 8K x 16 banks

– 512 Kilobit of memory on chip

Fast asynchronous address-to-data access time: 15ns

User-controlled input pins included for bank selects

Independent port controls with asynchronous address &

data busses

Four 16-bit mailboxes available to each port for inter-

processor communications; interrupt option

Interrupt flags with programmable masking

Dual Chip Enables allow for depth expansion without

external logic

and

are available for x8 or x16 bus matching

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)

Functional Block Diagram

MUX

R/W

8Kx16

MEMORY

ARRAY

(BANK 0)

MUX

I/O

8L-15L

I/O

0L-7L

I/O

CONTROL

MUX

8Kx16

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

8R-15R

I/O

0R-7R

R/W

CONTROL

LOGIC

CONTROL

LOGIC

12L

0L(1)

ADDRESS

DECODE

ADDRESS

DECODE

12R

0R(1)

BANK

DECODE

MUX

8Kx16

MEMORY

ARRAY

(BANK 3)

MUX

BANK

DECODE

BKSEL

3(2)

BKSEL

0(2)

BANK

SELECT

5L(1)

0L(1)

/UB

R/W

MAILBOX

INTERRUPT

LOGIC

5R(1)

0R(1)

/UB

R/W

MBSEL

INT

MBSEL

INT

3739 drw 01

NOTES:

1. The first six address pins for each port serve dual functions. When

MBSEL

= V

, the pins serve as memory address inputs. When

MBSEL

= V

, the pins

serve as mailbox address inputs.

2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for

more details.

MAY 2000

DSC 3739/6

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