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IDT707288S20PFG

Description
Dual-Port SRAM, 64KX16, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM, TQFP-100
Categorystorage    storage   
File Size126KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

IDT707288S20PFG Overview

Dual-Port SRAM, 64KX16, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM, TQFP-100

IDT707288S20PFG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instruction14 X 14 MM, 1.40 MM, TQFP-100
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time20 ns
Other featuresAUTOMATIC POWER-DOWN; LOW POWER STANDBY MODE; INTERRUPT FLAG
JESD-30 codeS-PQFP-G100
JESD-609 codee3
length14 mm
memory density1048576 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX16
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
Features
IDT707288S/L
64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
– Four independent 16K x 16 banks
– 1 Megabit of memory on chip
Fast asynchronous address-to-data access time: 15ns
User-controlled input pins included for bank selects
Independent port controls with asynchronous address &
data busses
Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
Interrupt flags with programmable masking
Dual Chip Enables allow for depth expansion without
external logic
UB
and
LB
are available for x8 or x16 bus matching
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)
Functional Block Diagram
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
D
E
D S
N N
E G
M SI
M E
O D
C
E W
R E
T N
O
N
MUX
CONTROL
LOGIC
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
MUX
CONTROL
LOGIC
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
I/O
8L-15L
I/O
0L-7L
I/O
CONTROL
I/O
CONTROL
A
13L
A
0L(1)
ADDRESS
DECODE
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
ADDRESS
DECODE
A
13R
A
0R(1)
BA
1L
BA
0L
BANK
DECODE
BANK
DECODE
BA
1R
BA
0R
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
BKSEL
3(2)
BKSEL
0(2)
BANK
SELECT
A
5L(1)
A
0L(1)
LB
L
/UB
L
OE
L
R/W
L
CE
L
MAILBOX
INTERRUPT
LOGIC
A
5R(1)
A
0R(1)
LB
R
/UB
R
OE
R
R/W
R
CE
R
MBSEL
L
INT
L
R
O
F
I/O
8R-15R
I/O
0R-7R
MBSEL
R
INT
R
,
3592 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as memory address inputs. When
MBSEL
= V
IL
, the pins
serve as mailbox address inputs.
2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for
more details.
MAY 2000
1
©2000 Integrated Device Technology, Inc.
DSC 3592/7
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