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IDT70914S25J

Description
Multi-Port SRAM, 4KX9, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
Categorystorage    storage   
File Size107KB,11 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70914S25J Overview

Multi-Port SRAM, 4KX9, 25ns, CMOS, PQCC68, PLASTIC, LCC-68

IDT70914S25J Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeLCC
package instructionPLASTIC, LCC-68
Contacts68
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time25 ns
Other featuresAUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.2062 mm
memory density36864 bit
Memory IC TypeMULTI-PORT SRAM
memory width9
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals68
word count4096 words
character code4000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4KX9
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum standby current0.015 A
Minimum standby current4.5 V
Maximum slew rate0.27 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width24.2062 mm
HIGH SPEED 36K (4K X 9)
SYNCHRONOUS
DUAL-PORT RAM
Features
x
IDT70914S
x
x
x
High-speed clock-to-data output times
– Military: 20/25ns (max.)
– Commercial: 12/15/20ns (max.)
Low-power operation
– IDT70914S
Active: 850 mW (typ.)
Standby: 50 mW (typ.)
Architecture based on Dual-Port RAM cells
– Allows full simultaneous access from both ports
Synchronous operation
– 4ns setup to clock, 1ns hold on all control, data, and address
inputs
– Data input, address, and control registers
x
x
x
x
x
x
x
– Fast 12ns clock to data out
– Self-timed write allows fast cycle times
– 16ns cycle times, 60MHz operation
TTL-compatible, single 5V (+ 10%) power supply
Clock Enable feature
Guaranteed data output hold times
Available in 68-pin PLCC, and 80-pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (-40°C to +85°C) is available
for selected speeds.
Recommended for replacement of IDT7099 (4K x 9) if
separate 9th bit data control signals are not required.
Functional Block Diagram
REGISTER
REGISTER
I/O
0-8L
WRITE
LOGIC
MEMOR
MEMORY
Y
ARRAY
ARRAY
WRITE
LOGIC
I/O
0-8R
SENSE
SENSE
AMPS DECODER DECODER AMPS
OE
L
CLK
L
CLKEN
L
Self-
timed
Write
Logic
REG
en
REG
en
OE
R
CLK
R
CLKEN
R
Self-
timed
Write
Logic
R/W
L
CE
L
REG
REG
R/W
R
CE
R
3490 drw 01
A
0L
-A
11L
A
0R
-A
11R
JANUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3490/6

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