November 2008
IM[S/H]H1GP03A1F1C
IM[S/H]H2GP[13/02]A1F1C
IM[S/H]H4GP[23/12]A1F1C
240-Pin DDR3 Registered Modules with Parity bit
1-GByte, 2-GByte and 4-GByte
EU RoHS Compliant
Advance
Internet Data Sheet
Rev. 0.63
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
IM[S/H]H1GP03A1F1C, IM[S/H]H2GP[13/02]A1F1C, IM[S/H]H4GP[23/12]A1F1C
Revision History: 2008-11, Rev. 0.63
Page
All
All
43 - 79
40 - 42
All
All
Subjects (major changes since last revision)
Editoral changes and adapted to internet edition.
Updated package outline, SPD codes, and editoral changes.
Updated SPD Codes.
Updated IDD values.
Added Product Types and related information for modules with Heat Spreader.
Data sheet for 1GB, 2GB and 4GB Registered Memory Modules with Parity bit Product Family.
Previous Revision: 2008-04, Rev. 0.62
Previous Revision: 2008-04, Rev. 0.61
Previous Revision: 2008-04, Rev. 0.60
Previous Revision: 2008-01, Rev. 0.51
Previous Revision: 2007-12, Rev. 0.5
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qag_techdoc_A4, 4.20, 2008-01-25
12122007-WJ2L-RGDP
2
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
1
Overview
This chapter gives an overview of the 240–pin Registered DDR3 Dual-In-Line Memory Modules product family with parity bit
for address and control bus and describes its main characteristics.
1.1
Features
• On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
• Refresh, Self Refresh and Power Down Modes.
• ZQ Calibration for output driver and ODT.
• System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
• Serial Presence Detect with EEPROM.
• On-DIMM Thermal Sensor.
• RDIMM dimensions: 133.35 mm x 30 mm.
• Based on standard reference raw cards: 'A', 'B', 'C', 'E' and
'H'
• RoHS compliant products
1)
.
• 240-pin 8-Byte DDR3 SDRAM Registered Dual-In-Line
Memory Modules with parity bit for address and control
bus.
• Module organization: One rank – 128M
×
72, 256M
×
72,
two rank – 256M
×
72, 512M
×
72 , four rank – 512M
×
72
Chip organization: 128M
×
8, 256M
×
4
• PC3-10600 and PC3-8500 module speed grades.
• 4-GB, 2-GB, 1-GB modules built with 1-Gbit DDR3
SDRAMs in packages PG-TFBGA-78
• DDR3 SDRAMs with a single 1.5 V (± 0.075 V) power
supply.
• Asynchronous Reset.
• Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
TABLE 1
Performance Table for DDR3–1600 and DDR3–1333
Qimonda Speed Code
Module Speed Bin
Device Speed Bin
CL-
n
RCD
-
n
RP
CL and CWL settings for maximum clock
frequency
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
PC3
DDR3
–13G
–10600G
–1333G
8-8-8
CL = 8
CWL = 7
667
1333
533
1066
–13H
–10600H
–1333H
9-9-9
CL = 9
CWL = 7
667
1333
533
1066
MHz
MHz
Mb/s
MHz
Mb/s
Unit
Note
2)
Rev. 0.63, 2008-11
12122007-WJ2L-RGDP
3
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 2
Performance Table for DDR3–1066 and DDR3–800
Qimonda Speed Code
Module Speed Bin
Device Speed Bin
CL-
n
RCD
-
n
RP
PC3
DDR3
–10F
–8500F
–1066F
7-7-7
–10G
–8500G
–1066G
8-8-8
CL = 8
CWL = 6
533
1066
400
800
MHz
MHz
Mb/s
MHz
Mb/s
Unit
Note
2)
CL and CWL settings for maximum clock frequency
CL = 7
CWL = 6
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
533
1066
400
800
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products.
2) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting. For details, refer to
Chapter 4.1
Speed Bins.
Rev. 0.63, 2008-11
12122007-WJ2L-RGDP
4
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
1.2
Description
a PLL for the clock distribution. De-coupling capacitors, stub
resistors, calibration resistors and termination resistors are
mounted on the PCB. The DIMMs feature serial presence
detect based on a 256 byte serial EEPROM device using the
2-pin I2C protocol. The first 176 bytes are programmed with
module specific SPD data.
The
Qimonda
IM[S/H]H[1G/2G/4G]PxxA1F1C
are
Registered DIMM (PDIMM) family with parity bit for address
and control bus and 30 mm height based on DDR3 SDRAM
technology. DIMMs are available in 128M
×
72 (1-GB),
256M
×
72 (2-GB), 512M
×
72 (4-GB) organization and
density, intended for mounting into 240-pin connector
sockets.
The memory array is designed with 1-Gbit Double-Data-Rate-
Three (DDR3) Synchronous DRAMs. All control and address
signals are re-driven on the DIMM using register devices and
TABLE 3
Product Information for Modules without Heat Spreader
Qimonda Product Type
Compliance Code
Description
1-GByte Registered DIMM IMSH1GP03A1F1C
IMSH1GP03A1F1C–10F
IMSH1GP03A1F1C–10G
IMSH1GP03A1F1C–13G
IMSH1GP03A1F1C–13H
1GB 1R×8 PC3–8500P–7-10–A0
1GB 1R×8 PC3–8500P–8-10–A0
1GB 1R×8 PC3–10600P–8-10–A0
1GB 1R×8 PC3–10600P–9-10–A0
240-pin 1-GByte DDR3 registered DIMM with one
rank and on-DIMM thermal sensor. The memory
rank consists of nine DDR3 components in x8
organization. Standard reference card A is used on
this assembly
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
240-pin 2-GByte DDR3 registered DIMM with two
ranks and on-DIMM thermal sensor. Each memory
rank consists of nine DDR3 components in x8
organization. Standard reference card B is used on
this assembly
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
240-pin 2-GByte DDR3 registered DIMM with one
rank and on-DIMM thermal sensor. The memory
rank consists of eighteen DDR3 components in x4
organization. Standard reference card C is used on
this assembly
Used DDR3 SDRAM Component
Product Type: IDSH1G-02A1F1C
Density: 1-Gbit
Organization: 256Mbit × 4
Address Bits (Row/Column/Bank): 14/11/3
2-GByte Registered DIMM IMSH2GP13A1F1C
IMSH2GP13A1F1C–10F
IMSH2GP13A1F1C–10G
IMSH2GP13A1F1C–13G
IMSH2GP13A1F1C–13H
2GB 2R×8 PC3–8500P–7-10–B0
2GB 2R×8 PC3–8500P–8-10–B0
2GB 2R×8 PC3–10600P–8-10–B0
2GB 2R×8 PC3–10600P–9-10–B0
2-GByte Registered DIMM IMSH2GP02A1F1C
IMSH2GP02A1F1C–10F
IMSH2GP02A1F1C–10G
IMSH2GP02A1F1C–13G
IMSH2GP02A1F1C–13H
2GB 1R×4 PC3–8500P–7-10–C0
2GB 1R×4 PC3–8500P–8-10–C0
2GB 1R×4 PC3–10600P–8-10–C0
2GB 1R×4 PC3–10600P–9-10–C0
Rev. 0.63, 2008-11
12122007-WJ2L-RGDP
5
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