IDT70T3399S200BFG datasheet, PDF

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IDT70T3399S200BFG: DescriptionDual-Port SRAM, 128KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208; Categorystorage storage; File Size304KB，28 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70T3399S200BFG Overview

Dual-Port SRAM, 128KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208

IDT70T3399S200BFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	10 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	15 mm
memory density	2359296 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	208
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX18
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm

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Features:

◆

HIGH-SPEED 2.5V

512/256/128K X 18

IDT70T3339/19/99S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

◆

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin

Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array

(fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG, Collision Detection and

Interrupt are not supported on the 144-pin TQFP package

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

0 1

L L

B B

1 0

R R

1/0

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

FT/PIPE

0/1

0a 1a 0b

0/1

FT/PIPE

512/256/128K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

18L

(1)

REPEAT

ADS

CNTEN

18R (1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

INTERRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1R

JTAG

TDO

COL

INT

(2)

COL

INT

CONTROL

LOGIC

(2)

5652 drw 01

NOTES:

1. Address A

is a NC for the IDT70T3319. Also, Addresses A

and A

are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

JULY 2008

DSC-5652/5

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