August 2008
IMSH1GS14A1F1C(T)
IMSH1GS03A1F1C(T)
IMSH2GS13A1F1C(T)
204-Pin Small-Outlined Dual-In-Line Memory Modules
1-GByte and 2-GByte
DDR3 SDRAM
EU RoHS compliant
Advance
Internet Data Sheet
Rev. 0.63
Advance Internet Data Sheet
IMSH[1G/2G]S[0/1][3/4]A1F1C(T)
DDR3 SO-DIMM Modules
IMSH1GS14A1F1C(T), IMSH1GS03A1F1C(T), IMSH2GS13A1F1C(T)
Revision History: 2008-08, Rev. 0.63
Page
21 - 65
All
19 - 65
All
All
Subjects (major changes since last revision)
Updated SPD codes and adapted to internet edition.
Added product type IMSH2GS13A1F1CT16H.
Updated SPD codes.
Editorial change.
Data sheet for 1GByte and 2GByte Small-Outlined DIMMs (with and without Thermal Sensor).
Previous Revision: 2008-05, Rev. 0.62
Previous Revision: 2008-05, Rev. 0.61
Previous Revision: 2008-01, Rev. 0.51
Previous Revision: 2007-11, Rev. 0.50
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qag_techdoc_A4, 4.20, 2008-01-25
01102008-EWLC-AP2C
2
Advance Internet Data Sheet
IMSH[1G/2G]S[0/1][3/4]A1F1C(T)
DDR3 SO-DIMM Modules
1
Overview
This chapter gives an overview of the 204–pin Small-Outlined DDR3 Dual-In-Line memory modules product family and
describes its main characteristics.
1.1
Features
• On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
• Refresh. Self Refresh and Power Down Modes.
• ZQ Calibration for output driver and ODT.
• System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
• Serial Presence Detect with EEPROM
• Thermal sensor functionality.
• SO-DIMM dimensions: 67.6 mm x 30 mm.
• Based on standard reference raw cards: 'A', 'B', 'C' and 'F'
• RoHS compliant products
1)
.
• 204-pin 8-Byte DDR3 SDRAM Small-Outlined Dual-In-
Line Memory Modules .
• Module organization: 128M
×
64, 256M
×
64
Chip organization: 64M
×
16, 128M
×
8.
• PC3-12800, PC3-10600, PC3-8500 and PC3-6400
module speed grades.
• 2-GB and 1-GB modules built with 1Gb DDR3 SDRAMs in
packages PG-TFBGA-78 and PG-TFBGA-96.
• DDR3 SDRAMs with a single 1.5 V (± 0.075 V) power
supply.
• Asynchronous Reset.
• Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
TABLE 1
Performance Table for DDR3–1600 and DDR3–1333
QAG Speed Code
Module Speed Bin
Device Speed Bin
CL-
n
RCD
-
n
RP
PC3–
DDR3–
–16H
–12800H
–1600H
9-9-9
–13G
10600G
1333G
8-8-8
CL = 8
CWL = 7
667
1333
533
1066
–13H
10600H
1333H
9-9-9
CL = 9
CWL = 7
667
1333
533
1066
–13J
10600J
1333J
10-10-10
CL = 10
CWL = 7
667
1333
533
1066
MHz
MHz
Mb/s
MHz
Mb/s
Unit
Note
1)
CL and CWL settings for maximum
CL = 9
clock frequency
CWL = 8
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
800
1600
667
1333
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting. For details, refer to
Chapter 4.1
Speed Bins.
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products
.
Rev. 0.63, 2008-08
01102008-EWLC-AP2C
3
Advance Internet Data Sheet
IMSH[1G/2G]S[0/1][3/4]A1F1C(T)
DDR3 SO-DIMM Modules
TABLE 2
Performance Table for DDR3–1066 and DDR3–800
QAG Speed Code
Module Speed Bin
Device Speed Bin
CL-
n
RCD
-
n
RP
CL and CWL settings for maximum
clock frequency
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
PC3–
DDR3–
–10F
8500F
1066F
7-7-7
CL = 7
CWL = 6
533
1066
400
800
–10G
8500G
1066G
8-8-8
CL = 8
CWL = 6
533
1066
400
800
–08D
6400D
800D
5-5-5
CL = 5
CWL = 5
400
800
300
600
–08E
6400E
800E
6-6-6
CL = 6
CWL = 5
400
800
300
600
MHz
MHz
Mb/s
MHz
Mb/s
Unit
Note
1)
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting. For details, refer to
Chapter 4.1
Speed Bins.
Rev. 0.63, 2008-08
01102008-EWLC-AP2C
4
Advance Internet Data Sheet
IMSH[1G/2G]S[0/1][3/4]A1F1C(T)
DDR3 SO-DIMM Modules
1.2
Description
The memory array is designed with 1Gb Double Data Rate
(DDR3) Synchronous DRAMs. De-coupling capacitors, stub
resistors, calibration resistors and termination resistors are
mounted on the PCB board. The DIMMs feature serial
presence detect based on a 256 byte serial EEPROM device
using the 2-pin I
2
C protocol. The first 176 bytes are
programmed with module specific SPD data.
The Qimonda IMSH[1G/2G]S[0/1][3/4]A1F1C(T) are Small-
Outlined DIMM (SO-DIMM) family with 30 mm height based
on DDR3 SDRAM technology. DIMMs are available in
128M
×
64 (1GB), 256M
×
64 (2GB) organization and
density, intended for mounting into 204 pin connector
sockets.
TABLE 3
Ordering Information Table for Modules with Thermal Sensor
QAG Part Number
Compliance Code
Description
1024 MByte Small-Outlined DIMM – IMSH1GS14A1F1CT
IMSH1GS14A1F1CT08D
IMSH1GS14A1F1CT08E
IMSH1GS14A1F1CT10F
IMSH1GS14A1F1CT10G
IMSH1GS14A1F1CT13G
IMSH1GS14A1F1CT13H
IMSH1GS14A1F1CT13J
1G 2R×16 PC3–6400S–5-10–A1
1G 2R×16 PC3–6400S–6-10–A1
1G 2R×16 PC3–8500S–7-10–A1
1G 2R×16 PC3–8500S–8-10–A1
1G 2R×16 PC3–10600S–8-10–A1
1G 2R×16 PC3–10600S–9-10–A1
1G 2R×16 PC3–10600S–10-10–A1
204-pin 1024 MByte DDR3 SO-DIMM with two
ranks and On-DIMM Thermal Sensor. Memory rank
consists of four DDR3 components in x16
organization. Standard reference card A is used on
this assembly
Used DDR3 SDRAM Component
Part Number: IDSH1G-04A1F1C
Density: 1Gbit
Organization: 64Mbit × 16
Address Bits (Row/Column/Bank): 13/10/3
204-pin 1024 MByte DDR3 SO-DIMM with one rank
and On-DIMM Thermal Sensor. Memory rank
consists of eight DDR3 components in x8
organization. Standard reference card B is used on
this assembly
Used DDR3 SDRAM Component
Part Number: IDSH1G-03A1F1C
Density: 1Gbit
Organization: 128Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
204-pin 2048 MByte DDR3 SO-DIMM with two
ranks and On-DIMM Thermal Sensor. Memory rank
consists of eight DDR3 components in x8
organization. Standard reference card F is used on
this assembly
Used DDR3 SDRAM Component
Part Number: IDSH1G-03A1F1C
Density: 1Gbit
Organization: 128Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
1024 MByte Small-Outlined DIMM – IMSH1GS03A1F1CT
IMSH1GS03A1F1CT08D
IMSH1GS03A1F1CT08E
IMSH1GS03A1F1CT10F
IMSH1GS03A1F1CT10G
IMSH1GS03A1F1CT13G
IMSH1GS03A1F1CT13H
IMSH1GS03A1F1CT13J
1G 1R×8 PC3–6400S–5-10–B1
1G 1R×8 PC3–6400S–6-10–B1
1G 1R×8 PC3–8500S–7-10–B1
1G 1R×8 PC3–8500S–8-10–B1
1G 1R×8 PC3–10600S–8-10–B1
1G 1R×8 PC3–10600S–9-10–B1
1G 1R×8 PC3–10600S–10-10–B1
2048 MByte Small-Outlined DIMM – IMSH2GS13A1F1CT
IMSH2GS13A1F1CT08D
IMSH2GS13A1F1CT08E
IMSH2GS13A1F1CT10F
IMSH2GS13A1F1CT10G
IMSH2GS13A1F1CT13G
IMSH2GS13A1F1CT13H
IMSH2GS13A1F1CT13J
IMSH2GS13A1F1CT16H
2G 2R×8 PC3–6400S–5-10–F0
2G 2R×8 PC3–6400S–6-10–F0
2G 2R×8 PC3–8500S–7-10–F0
2G 2R×8 PC3–8500S–8-10–F0
2G 2R×8 PC3–10600S–8-10–F0
2G 2R×8 PC3–10600S–9-10–F0
2G 2R×8 PC3–10600S–10-10–F0
2G 2R×8 PC3–12800S–9-10–F0
Rev. 0.63, 2008-08
01102008-EWLC-AP2C
5
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