IDT70T3399S200DD datasheet, PDF

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IDT70T3399S200DD: DescriptionDual-Port SRAM, 128KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144; Categorystorage storage; File Size472KB，28 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70T3399S200DD Overview

Dual-Port SRAM, 128KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144

IDT70T3399S200DD Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
Contacts	144
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	10 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
length	20 mm
memory density	2359296 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Number of functions	1
Number of terminals	144
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	20 mm

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HIGH-SPEED 2.5V

PRELIMINARY

512/256/128K X 18

IDT70T3339/19/99S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

◆

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin

Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array

(fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG, Collision Detection and

Interrupt are not supported on the 144-pin TQFP package

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

/PIPE

R/W

1/0

B B

0 1

L L

B B

1 0

R R

1/0

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

FT/PIPE

0/1

0a 1a 0b

0/1

/PIPE

512/256/128K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

18L(1)

REPEAT

ADS

CNTEN

18R(1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

INTERRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1 R

JTAG

TDO

COL

INT

COL

INT

(2)

CONTROL

LOGIC

(2)

5652 drw 01

NOTES:

1. Address A

is a NC for the IDT70T3319. Also, Addresses A

and A

are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

NOVEMBER 2003

DSC-5652/3

IDT70T3399S200DD Related Products

	IDT70T3399S200DD	IDT70T3339S166DDI	IDT70T3339S166BFI	IDT70T3399S166BFI	IDT70T3319S166BFI	IDT70T3319S200DD	IDT70T3339S200DD	IDT70T3339S200BF	IDT70T3319S200BF	IDT70T3399S200BF
Description	Dual-Port SRAM, 128KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 512KX18, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 512KX18, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 128KX18, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 256KX18, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 256KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 512KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 512KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 256KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 128KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	QFP	QFP	BGA	BGA	BGA	QFP	QFP	BGA	BGA	BGA
package instruction	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	TFBGA,	TFBGA,	TFBGA,	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	TFBGA,	TFBGA,	TFBGA,
Contacts	144	144	208	208	208	144	144	208	208	208
Reach Compliance Code	compliant	not_compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	10 ns	12 ns	12 ns	12 ns	12 ns	10 ns	10 ns	10 ns	10 ns	10 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-PQFP-G144	S-PQFP-G144	S-PBGA-B208	S-PBGA-B208	S-PBGA-B208	S-PQFP-G144	S-PQFP-G144	S-PBGA-B208	S-PBGA-B208	S-PBGA-B208
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
length	20 mm	20 mm	15 mm	15 mm	15 mm	20 mm	20 mm	15 mm	15 mm	15 mm
memory density	2359296 bit	9437184 bit	9437184 bit	2359296 bit	4718592 bit	4718592 bit	9437184 bit	9437184 bit	4718592 bit	2359296 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	18	18	18	18	18	18	18	18	18	18
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of terminals	144	144	208	208	208	144	144	208	208	208
word count	131072 words	524288 words	524288 words	131072 words	262144 words	262144 words	524288 words	524288 words	262144 words	131072 words
character code	128000	512000	512000	128000	256000	256000	512000	512000	256000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	85 °C	85 °C	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	128KX18	512KX18	512KX18	128KX18	256KX18	256KX18	512KX18	512KX18	256KX18	128KX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	TFBGA	TFBGA	TFBGA	LFQFP	LFQFP	TFBGA	TFBGA	TFBGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	225	225	225	225	225	225	225	225	225	225
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.2 mm	1.2 mm	1.2 mm	1.6 mm	1.6 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V
Minimum supply voltage (Vsup)	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	BALL	BALL	BALL	GULL WING	GULL WING	BALL	BALL	BALL
Terminal pitch	0.5 mm	0.5 mm	0.8 mm	0.8 mm	0.8 mm	0.5 mm	0.5 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD	BOTTOM	BOTTOM	BOTTOM	QUAD	QUAD	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	30	20	20	20	20	20	20	20	20
width	20 mm	20 mm	15 mm	15 mm	15 mm	20 mm	20 mm	15 mm	15 mm	15 mm
Is it lead-free?	Contains lead	-	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Maker	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Humidity sensitivity level	-	4	3	3	3	-	-	3	3	3

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