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IDT70T651S12DR8

Description
Multi-Port SRAM, 256KX36, 12ns, CMOS, PQFP208
Categorystorage    storage   
File Size232KB,27 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70T651S12DR8 Overview

Multi-Port SRAM, 256KX36, 12ns, CMOS, PQFP208

IDT70T651S12DR8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
Maximum access time12 ns
I/O typeCOMMON
JESD-30 codeS-PQFP-G208
JESD-609 codee0
memory density9437184 bit
Memory IC TypeMULTI-PORT SRAM
memory width36
Number of ports2
Number of terminals208
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5,2.5/3.3 V
Certification statusNot Qualified
Maximum standby current0.01 A
Minimum standby current2.4 V
Maximum slew rate0.355 mA
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Features
HIGH-SPEED 2.5V
256/128K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
IDT70T651/9S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T651/9 easily expands data bus width to 72 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
Flatpack and 208-ball fine pitch Ball Grid Array.
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
BE
3R
BE
2R
BE
1R
BE
0R
R/
W
L
CE
0L
CE
1L
BB
EE
01
LL
BB
EE
23
LL
BBBB
EEEE
3210
R RRR
R/
W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
OE
R
256/128K x 36
MEMORY
ARRAY
I/O
0L-
I/O
35L
Di n_L
Di n_R
I/O
0R -
I/O
35R
A
17L(1)
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
17R(1)
A
0R
CE
0L
CE
1L
OE
L
R/W
L
BUSY
L (2,3)
SEM
L
INT
L(3)
ZZ
L
(4)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
R/W
R
CE
0R
CE
1R
TDI
TD O
JTAG
TC K
TMS
TRST
M/S
BUSY
R(2,3)
SEM
R
INT
R(3)
ZZ
R
(4)
NOTES:
1. Address A
17x
is a NC for IDT70T659.
2.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
3.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,
INTx,
M/S and the sleep
mode pins themselves (ZZx) are not affected during sleep mode.
ZZ
CONTROL
LOGIC
4869 drw 01
JANUARY 2006
DSC-5632/5
1
©2006 Integrated Device Technology, Inc.
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