TECHNICAL NOTE
High-performance Clock Generator Series
3ch Clock Generator
for Digital Cameras
BU2394KN,BU2396KN
●Description
These clock generators are an IC generating three types of clocks – CCD, USB, and VIDEO clocks – necessary for digital
still camera systems and digital video camera systems, with a single chip through making use of the PLL technology.
Generating these clocks with a single chip allows for the simplification of clock system, little space occupancy, reduction in
the number of components used for mobile camera equipment, which is becoming increasingly downsized and less costly.
●Features
1) Connecting a crystal oscillator generates multiple clock signals with a built-in PLL.
2) The CCD clock provides switching selection outputs.
3) Providing the output of low period-jitter clock.
4) Incorporating compact package VQFN20 most suited for mobile devices.
5) Single power supply of 3.3 V
●Applications
Generation of clocks used in digital still camera and digital video camera systems
●Lineup
BU2394KN
Supply voltage
Operating temperature range
Reference input clock
Output CCD clock
3.0V½3.6V
-5½＋70℃
14.318182MHz
28.636363MHz
135.000000MHz
110.000000MHz
108.000000MHz
98.181818MHz
Output USB clock
Output VIDEO clock
48.008022MHz
14.318182MHz
17.734450MHz
27.000000MHz
12.000000MHz
36.000000MHz
30.000000MHz
24.000000MHz
BU2396KN
3.0V½3.6V
-5½＋70℃
12.000000MHz
●
Absolute Maximum Ratings（Ta=25℃）
Parameter
Supply voltage
Input voltage
Storage Temperature range
Symbol
VDD
VIN
Tstg
PD
Limit
-0.5½7.0
-0.5½VDD+0.5
-30½125
530
Unit
Ｖ
Ｖ
℃
mW
Power dissipation
*1 Operating temperature is not guaranteed.
*2 In the case of exceeding Ta = 25℃, 5.3mW should be reduced per 1℃.
*3 The radiation-resistance design is not carried out.
*4 Power dissipation is measured when the IC is mounted to the printed circuit board.
Sep. 2008
●Recommended
Operating Range
Parameter
Supply voltage
Input H voltage
Input L voltage
Operating temperature
Output load
●
Symbol
VDD
VINH
VINL
Topr
CL
Limit
3.0½3.6
0.8VDD½VDD
0.0½0.2VDD
-5½70
15(MAX)
Unit
Ｖ
Ｖ
Ｖ
℃
pF
Electrical characteristics
BU2394KN(VDD=3.3V, Ta=25℃, unless otherwise specified.)
XTAL_SEL=H with crystal oscillator at a frequency of 28.636363 MHz, while XTAL_SEL=L at 14.318182 MHz
Parameter
Symbol
IDD
VOH1
VOH2
VOHR
VOL1
VOL2
VOLR
Limit
Min.
－
VDD-0.5
VDD-0.5
VDD-0.5
－
－
－
Typ.
45
VDD-0.2
VDD-0.2
VDD-0.2
0.2
0.2
0.2
Max.
60
－
－
－
0.5
0.5
0.5
Unit
mA
V
V
V
V
V
V
At no load
When current load = - 9.0mA
When current load = - 7.0mA
When current load = - 4.5mA
When current load =11mA
When current load =9.0mA
When current load =5.5mA
Specified by a current value
running when a voltage of 0V is
applied to a measuring pin.
(R=VDD／I)
XTAL×(1188/63)/2
XTAL×(1056/70)/2
XTAL×(864/63)/2
XTAL×(968/63)/2
XTAL×(228/17)/4
XTAL Output
XTAL×(706/57)/10
Measured at a voltage of 1/2 of
VDD
Measured at a voltage of 1/2 of
VDD
Period of transition time required
for the output to reach 80% from
20% of VDD.
Period of transition time required
for the output to reach 20% from
80% of VDD.
※1
※2
Condition
【Action
circuit current】
【Output
H voltage】
CLK1
CLK2
REF_CLK
【Output
L voltage】
CLK1
CLK2
REF_CLK
【Pull-Up
resistance value】
FS1, FS2, FS3,
CLK2ON, XTAL_SEL
Pull-Up
R
125
250
375
Ω
【Output
frequency】
CLK1 FS2:H FS3:H
CLK1 FS2:H FS3:L
CLK1 FS2:L FS3:L
CLK1 FS2:L FS3:H
CLK2
REF_CLK FS1:H
REF_CLK FS1:L
【Output
waveform】
Duty1 100MHz or less
Duty2 100MHz or more
Rise time
Tr
Fall time
Tf
【Jitter】
Period-Jitter 1σ
Period-Jitter MIN-MAX
P-J1σ
P-J
MIN-MAX
－
－
30
180
－
－
psec
psec
－
2.5
－
nsec
－
2.5
－
nsec
Duty1
Duty2
45
－
50
50
55
－
％
％
Fclk1-1
Fclk1-2
Fclk1-3
Fclk1-4
Fclk2-2
Fref1-1
Fref1-2
－
－
－
－
－
－
－
135.000000
108.000000
98.181818
110.000000
48.008022
14.318182
17.734450
－
－
－
－
－
－
－
MHz
MHz
MHz
MHz
MHz
MHz
MHz
【Output
Lock-Time】
Tlock
－
－
1
msec
※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN. If the
input frequency is set to values shown below, the output frequency will be as listed above.
When XTAL_SEL is set to H, the input frequency on XTALIN will be 28.636363 MHz.
When XTAL_SEL is set to L, the input frequency on XTALIN will be 14.318182 MHz.
2/16
BU2396N(VDD=3.3V, Ta=25℃, Crystal =12.000000MHz, unless otherwise specified.)
Parameter
【Action
circuit current】
【Output
H voltage】
TGCLK
VCLK
UCLK
【Output
L voltage】
TGCLK
VCLK
UCLK
【Pull-Up
resistance value】
TGCLK_SEL1
TGCLK_SEL2
Pull-up
R
Specified by a current value
running when a voltage of 0V is
applied to a measuring pin.
(R=VDD／I)
Specified by a current value
running when a VDD is applied to
a measuring pin.
(R=VDD／I)
XTAL×(48/4)/6
XTAL×(60/4)/6
XTAL×(54/3)/6
XTAL×(54/3)/8
XTAL output
Measured at a voltage of 1/2 of VDD
Symbol
IDD
VOHT
VOHV
VOHU
VOLT
VOLV
VOLU
Limit
Min.
－
VDD-0.5
VDD-0.5
VDD-0.5
－
－
－
Typ.
23
－
－
－
－
－
－
Max.
35
－
－
－
0.5
0.5
0.5
Unit
mA
V
V
V
V
V
V
At no load
Condition
When current load =-5.0mA
When current load =-5.0mA
When current load =-5.0mA
When current load =5.0mA
When current load =5.0mA
When current load =5.0mA
125
250
375
KΩ
【Pull-Down
resistance value】
TGCLK_EN, TGCLK_PD
VCLK_EN, VCLK_PD
Pull-down
R
25
50
75
KΩ
【Output
frequency】
TGCLK
TGCLK
TGCLK
VCLK
UCLK
【Output
waveform】
Duty
Rise time
Tr
Fall time
Tf
【Jitter】
Period-Jitter 1σ
Period-Jitter MIN-MAX
【Output
Lock-Time】
P-J1σ
P-J
MIN-MAX
50
300
psec
psec
※1
※2
2.0
nsec
2.0
nsec
Duty
45
50
55
％
Period of transition time required
for the output to reach 80% from
20% of VDD.
Period of transition time required
for the output to reach 20% from
80% of VDD.
SEL1:L SEL2:L
SEL1:L SEL2:H
SEL1:H
TGCLK1
TGCLK2
TGCLK3
VCLK
UCLK
24.000000
30.000000
36.000000
27.000000
12.000000
MHz
MHz
MHz
MHz
MHz
Tlock
1
msec
※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 12.000000MHz, the output frequency will be as listed above.
Common to BU2394KN, BU2396KN
※1
Period-Jitter 1σ
This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※2
Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※3
Output Lock-Time
The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is switched from
Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency,
respectively.
3/16
●Reference
data (BU2394KN basic data)
RBW=1KHz
VBW=100Hz
10dB／div
500psec／div
Fig.2 135MHz Period-Jitter
At VDD=3.3V and CL=15pF
1.0V／div
1.0V／div
1.0nsec／div
Fig.1 135MHz output wave
At VDD=3.3V and CL=15pF
10KHz／div
Fig.3 135MHz Spectrum
At VDD=3.3V and CL=15pF
RBW=1KHz
VBW=100Hz
10dB／div
500psec／div
Fig.5 110MHz Period-Jitter
At VDD=3.3V and CL=15pF
1.0V／div
1.0V／div
2.0nsec／div
Fig.4 110MHz output wave
At VDD=3.3V and CL=15pF
10KHz／div
Fig.6 110MHz Spectrum
At VDD=3.3V and CL=15pF
RBW=1KHz
VBW=100Hz
10dB／div
500psec／div
Fig.8 108MHz Period-Jitter
At VDD=3.3V and CL=15pF
1.0V／div
1.0V／div
2.0nsec／div
Fig.7 108MHz output wave
At VDD=3.3V and CL=15pF
10KHz／div
Fig.9 108MHz Spectrum
At VDD=3.3V and CL=15pF
RBW=1KHz
VBW=100Hz
10dB／div
500psec／div
Fig.11 98MHz Period-Jitter
At VDD=3.3V and CL=15pF
1.0V／div
1.0V／div
2.0nsec／div
Fig.10 98MHz output wave
At VDD=3.3V and CL=15pF
10KHz／div
Fig.12 98MHz Spectrum
At VDD=3.3V and CL=15pF
4/16
●Reference
data (BU2394KN basic data)
RBW=1KHz
VBW=100Hz
10dB／div
500psec／div
Fig.14 48MHz Period-Jitter
At VDD=3.3V and CL=15pF
1.0V／div
1.0V／div
5.0nsec／div
Fig.13 48MHz output wave
At VDD=3.3V and CL=15pF
10KHz／div
Fig.15 48MHz Spectrum
At VDD=3.3V and CL=15pF
RBW=1KHz
VBW=100Hz
10dB／div
500psec／div
Fig.17 17.7MHz Period-Jitter
At VDD=3.3V and CL=15pF
1.0V／div
1.0V／div
10.0nsec／div
Fig.16 17.7MHz output wave
At VDD=3.3V and CL=15pF
10KHz／div
Fig.18 17.7MHz Spectrum
At VDD=3.3V and CL=15pF
RBW=1KHz
VBW=100Hz
10dB／div
500psec／div
Fig.20 14.3MHz Period-Jitter
At VDD=3.3V and CL=15pF
1.0V／div
1.0V／div
10.0nsec／div
Fig.19 14.3MHz output wave
At VDD=3.3V and CL=15pF
10KHz／div
Fig.21 14.3MHz Spectrum
At VDD=3.3V and CL=15pF
5/16
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