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IDT71128S20YI8

Description
Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
Categorystorage    storage   
File Size79KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT71128S20YI8 Overview

Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

IDT71128S20YI8 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSOJ
package instruction0.400 INCH, PLASTIC, SOJ-32
Contacts32
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.B
Maximum access time20 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
JESD-609 codee0
length20.955 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width4
Humidity sensitivity level3
Number of functions1
Number of terminals32
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.44
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height3.683 mm
Maximum standby current0.01 A
Minimum standby current4.5 V
Maximum slew rate0.145 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm
CMOS Static RAM
1 Meg (256K x 4-Bit)
Revolutionary Pinout
Features
x
x
IDT71128
Description
The IDT71128 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability CMOS technology. This state-of-the-art
technology, combined with innovative circuit design techniques,
provides a cost-effective solution for high-speed memory needs.
The JEDEC centerpower/GND pinout reduces noise generation
and improves system performance.
The IDT71128 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71128 are TTL-compat-
ible and operation is from a single 5V supply. Fully static asyn-
chronous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.
x
x
x
x
x
256K x 4 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
Equal access and cycle times
— Commercial and Industrial: 12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A
0
ADDRESS
DECODER
1,048,576-BIT
MEMORY
ARRAY
.
A
17
4
4
I/O
0
- I/O
3
I/O CONTROL
CS
WE
OE
CONTROL
LOGIC
3483 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3483/09
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