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FEATURES
Monolithic 14-Bit, 1.25 MSPS A/D Converter
Low Power Dissipation: 60 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 78.0 dB
Spurious-Free Dynamic Range: 88.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Pin MQFP
VINA
VINB
CML
CAPT
CAPB
VREF
SENSE
Complete 14-Bit, 1.25 MSPS
Monolithic A/D Converter
AD9241
FUNCTIONAL BLOCK DIAGRAM
CLK
SHA
MDAC1
GAIN = 16
A/D
MDAC2
GAIN = 8
A/D
MDAC3
GAIN = 8
A/D
AVDD
DVDD
DRVDD
5
4
4
A/D
5
4
14
OUTPUT BUFFERS
4
4
DIGITAL CORRECTION LOGIC
OTR
BIT 1
(MSB)
MODE
SELECT
1V
AD9241
REFCOM
AVSS
DVSS
DRVSS
BIT 14
(LSB)
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9241 is a 1.25 MSPS, single supply, 14-bit analog-to-
digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer-
ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9241 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and data-
acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9241 performs well in communication systems employ-
ing Direct-IF Down Conversion since the SHA in the differen-
tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 0.625 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
The AD9241 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-pin Metric Quad
Flatpack.
Low Power and Single Supply
The AD9241 consumes only 60 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9241 provides no missing codes, and excellent tempera-
ture drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9241 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single-ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD9241–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
MAX CONVERSION RATE
INPUT REFERRED NOISE
VREF = 1 V
VREF = 2.5 V
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL
1
DNL
1
No Missing Codes
Zero Error (@ +25°C)
Gain Error (@ +25°C)
2
Gain Error (@ +25°C)
3
TEMPERATURE DRIFT
Zero Error
Gain Error
2
Gain Error
3
POWER SUPPLY REJECTION
ANALOG INPUT
Input Span (with VREF = 1.0 V)
Input Span
(with VREF = 2.5 V)
Input (VINA or VINB) Range
Input Capacitance
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2.5 V Mode)
Output Voltage Tolerance (2.5 V Mode)
Load Regulation
4
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DVDD
DRVDD
Supply Current
IAVDD
IDRVDD
IDVDD
POWER CONSUMPTION
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
SAMPLE
= 1.25 MSPS, VREF = 2.5 V, VINB = 2.5 V,
T
MIN
to T
MAX
unless otherwise noted)
AD9241
14
1.25
0.9
0.36
±
2.5
±
0.6
±
1.0
±
2.5
±
0.7
14
0.3
1.5
0.75
3.0
20.0
5.0
0.1
2
5
0
AVDD
16
1
±
14
2.5
±
35
5.0
5
Units
Bits min
MHz min
LSB rms typ
LSB rms typ
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
Bits Guaranteed
% FSR max
% FSR max
% FSR max
ppm/°C typ
ppm/°C typ
ppm/°C typ
% FSR max
V p-p min
V p-p max
V min
V max
pF typ
Volts typ
mV max
Volts typ
mV max
mV max
kΩ typ
+5
+5
+5
13.0
1.0
3.0
65
85
V (± 5% AVDD Operating)
V (± 5% DVDD Operating)
V (± 5% DRVDD Operating)
mA max (10 mA typ )
mA max (1 mA typ )
mA max (2 mA typ )
mW typ
mW max
NOTES
1
VREF =1 V.
2
Including internal reference.
3
Excluding internal reference.
4
Load regulation with 1 mA load current (in addition to that required by the AD9241).
Specification subject to change without notice.
–2–
REV. 0
AD9241
AC SPECIFICATIONS
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
SAMPLE
= 1.25 MSPS, VREF = 2.5 V, A
IN
= –0.5 dBFS, AC Coupled/
Differential Input, T
MIN
to T
MAX
unless otherwise noted)
AD9241
78.0
74.5
77.0
12.7
12.1
12.5
79.0
75.5
79.0
–88.0
–77.5
–88.0
88.0
86.0
25
25
1
4
240
167
Units
dB typ
dB min
dB typ
Bits typ
Bits min
Bits typ
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB typ
MHz typ
MHz typ
ns typ
ps rms typ
ns typ
ns typ
Parameter
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
f
INPUT
= 100 kHz
f
INPUT
= 500 kHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
INPUT
= 100 kHz
f
INPUT
= 500 kHz
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT
= 100 kHz
f
INPUT
= 500 kHz
TOTAL HARMONIC DISTORTION (THD)
f
INPUT
= 100 kHz
f
INPUT
= 500 kHz
SPURIOUS FREE DYNAMIC RANGE
f
INPUT
= 100 kHz
f
INPUT
= 500 kHz
DYNAMIC PERFORMANCE
Full Power Bandwidth
Small Signal Bandwidth
Aperture Delay
Aperture Jitter
Acquisition to Full-Scale Step (0.0025%)
Overvoltage Recovery Time
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(AVDD = +5 V, DVDD = +5 V, T
Parameters
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
IN
= DVDD)
Low Level Input Current (V
IN
= 0 V)
Input Capacitance
LOGIC OUTPUTS (with DRVDD = 5 V)
High Level Output Voltage (I
OH
= 50
µA)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
µA)
Output Capacitance
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50
µA)
Low Level Output Voltage (I
OL
= 50
µA)
Specifications subject to change without notice.
MIN
to T
MAX
unless otherwise noted)
AD9241
+3.5
+1.0
±
10
±
10
5
+4.5
+2.4
+0.4
+0.1
5
+2.4
+0.7
Units
V min
V max
µA
max
µA
max
pF typ
V min
V min
V max
V max
pF typ
V min
V max
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OH
V
OL
V
OL
C
OUT
V
OH
V
OL
REV. 0
–3–
AD9241
SWITCHING SPECIFICATIONS
Parameters
Clock Period
1
CLOCK Pulse Width High
CLOCK Pulse Width Low
Output Delay
(T
MIN
to T
MAX
with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, C
L
= 20 pF)
Symbol
t
C
t
CH
t
CL
t
OD
AD9241
800
360
360
8
13
19
3
Units
ns min
ns min
ns min
ns min
ns typ
ns max
Clock Cycles
Pipeline Delay (Latency)
NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25
°C.
Specifications subject to change without notice.
S1
ANALOG
INPUT
THERMAL CHARACTERISTICS
S2
t
C
t
CH
t
CL
S4
S3
INPUT
CLOCK
Thermal Resistance
44-Pin MQFP
θ
JA
= 53.2°C/W
θ
JC
= 19°C/W
ORDERING GUIDE
DATA 1
t
OD
DATA
OUTPUT
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Model
AD9241AS
AD9241EB
Temperature
Range
–40
o
C to +85
o
C
Evaluation Board
Package
Description
44-Pin MQFP
Package
Option*
S-44
Parameter
AVDD
DVDD
AVSS
AVDD
DRVDD
DRVSS
REFCOM
CLK
Digital Outputs
VINA, VINB
VREF
SENSE
CAPB, CAPT
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
With
Respect
to
Min
AVSS
DVSS
DVSS
DVDD
DRVSS
AVSS
AVSS
DVSS
DRVSS
AVSS
AVSS
AVSS
AVSS
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
*S = Metric Quad Flatpack.
Max
+6.5
+6.5
+0.3
+6.5
+6.5
+0.3
+0.3
DVDD + 0.3
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+150
+150
+300
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
PIN CONNECTION
VINB
VINA
CML
CAPB
CAPT
NC
NC
NC
NC
44 43 42 41 40 39 38 37 36 35 34
DVSS 1
AVSS 2
DVDD 3
AVDD 4
DRVSS 5
DRVDD 6
CLK 7
NC 8
NC 9
NC 10
(LSB) BIT 14 11
12 13 14 15 16 17 18 19 20 21 22
PIN 1
IDENTIFIER
NC
NC
33 REFCOM
32 VREF
31 SENSE
30 NC
29 AVSS
28 AVDD
27 NC
26 NC
25 OTR
24 BIT 1 (MSB)
23 BIT 2
AD9241
TOP VIEW
(Not to Scale)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
BIT 9
BIT 8
BIT 13
BIT 7
BIT 6
BIT 5
BIT 4
BIT 12
BIT 11
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9241 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
BIT 10
WARNING!
ESD SENSITIVE DEVICE
–4–
BIT 3
REV. 0
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