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CMOS 300 MSPS Complete DDS
AD9852
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) A
OUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and on/off
output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
frequency hold function
Frequency ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interface
10 MHz serial 2-wire or 3-wire SPI-compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
SYSTEM CLOCK
DDS CORE
REFERENCE
CLOCK IN
REFCLK
BUFFER
4× TO 20×
REFCLK
MULTIPLIER
12
I
17
17
INV
SINC
FILTER
DIGITAL MULTIPLIERS
12
12-BIT
COSINE
DAC
MUX
FREQUENCY
ACCUMULATOR
ACC 1
PHASE
ACCUMULATOR
ACC 2
48
48
PHASE-TO-
AMPLITUDE
CONVERTER
ANALOG
OUT
DAC R
SET
MUX
DIFF/SINGLE
SELECT
SYSTEM
CLOCK
12-BIT
CONTROL
DAC
12
MUX
SYSTEM
CLOCK
48
14
Q
ANALOG
OUT
DEMUX
FSK/BPSK/HOLD
DATA IN
3
MUX
DELTA
FREQUENCY
RATE TIMER
2
48 SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
48
48
14
FIRST 14-BIT
PHASE/OFFSET
WORD
MUX
MUX
SYSTEM
CLOCK
14
SECOND 14-BIT
PHASE/OFFSET
WORD
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
12
AM
12-BIT DC
MODULATION CONTROL
ANALOG
IN
COMPARATOR
CLOCK
OUT
FREQUENCY FREQUENCY
TUNING
TUNING
WORD 2
WORD 1
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
MODE SELECT
SYSTEM
CLK
CLOCK
Q
D
INT
EXT
PROGRAMMING REGISTERS
÷2
SYSTEM
CLOCK
OSK
BUS
I/O PORT BUFFERS
GND
+V
S
AD9852
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
READ
WRITE
SERIAL/
PARALLEL
SELECT
Figure 1.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.
00634-001
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
AD9852
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Overview........................................................................................ 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
Explanation of Test Levels ........................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 12
Typical Applications ....................................................................... 16
Modes of Operation ....................................................................... 18
Single Tone (Mode 000)............................................................. 18
Unramped FSK (Mode 001)...................................................... 19
Ramped FSK (Mode 010) .......................................................... 19
Chirp (Mode 011)....................................................................... 22
BPSK (Mode 100) ....................................................................... 26
Using the AD9852 .......................................................................... 27
Internal and External Update Clock ........................................ 27
On/Off Output Shaped Keying (OSK) .................................... 27
Cosine DAC ................................................................................ 29
Control DAC ............................................................................... 29
Inverse Sinc Function ................................................................ 29
REFCLK Multiplier .................................................................... 29
High Speed Comparator............................................................ 30
Power-Down ............................................................................... 30
Programming the AD9852............................................................ 31
MASTER RESET ........................................................................ 31
Parallel I/O Operation ............................................................... 31
Serial Port I/O Operation.......................................................... 31
General Operation of the Serial Interface ................................... 34
Instruction Byte .......................................................................... 34
Serial Interface Port Pin Descriptions ..................................... 35
MSB/LSB Transfers .................................................................... 35
Control Register Descriptions .................................................. 36
Power Dissipation and Thermal Considerations ....................... 38
Thermal Impedance................................................................... 38
Junction Temperature Considerations .................................... 38
Evaluation of Operating Conditions............................................ 40
Thermally Enhanced Package Mounting Guidelines............ 40
Evaluation Board ............................................................................ 41
Evaluation Board Instructions.................................................. 41
General Operating Instructions ............................................... 41
Using the Provided Software .................................................... 43
Support ........................................................................................ 43
Outline Dimensions ....................................................................... 51
Ordering Guide .......................................................................... 52
Rev. E | Page 2 of 52
AD9852
REVISION HISTORY
5/07—Rev. D to Rev. E
Changed AD9852ASQ to AD9852ASVZ ....................... Universal
Changed AD9852AST to AD9852ASTZ......................... Universal
Change to Features............................................................................1
Changes to Endnote 10 of Table 1...................................................7
Changes to Absolute Maximum Ratings........................................8
Added Thermal Resistance Section ................................................8
Change to Ramped FSK (Mode 010) Section..............................19
Change to Internal and External Update Clock Section............27
Change to Thermal Impedance Section.......................................38
Changes to Junction Temperature Considerations Section.......38
Changes to Thermally Enhanced Package Mounting
Guidelines Section......................................................................40
Deleted Figure 61 to Figure 64 ......................................................41
Changes to Table 14 ........................................................................44
Updated Outline Dimensions........................................................51
Changes to Ordering Guide...........................................................52
12/05—Rev. C to Rev. D
Updated Format.................................................................. Universal
Changes to General Description .....................................................4
Changes to Explanation of Test Levels Section .............................9
Change to Pin Configuration ........................................................10
Changes to Figure 65 ......................................................................47
Changes to Outline Dimensions ...................................................52
Changes to Ordering Guide...........................................................52
4/04—Rev. B to Rev. C
Updated Format.................................................................. Universal
Changes to Figure 1...........................................................................1
Changes to General Description .....................................................3
Changes to Table 1 ............................................................................4
Changes to Footnote 2 ......................................................................6
Changes to Figure 2...........................................................................8
Changes to Table 5 ..........................................................................17
Changes to Equation in Ramped FSK (Mode 010).....................19
Changes to Evaluation Board Instructions ..................................39
Changes to General Operating Instructions Section..................39
Changes to Using the Provided Software Section.......................42
Changes to Figure 65 ......................................................................43
Changes to Figure 66 ......................................................................44
Changes to Figure 72 and Figure 73 .............................................48
Changes to Ordering Guide...........................................................48
3/02—Rev. A to Rev. B
Changes to General Description .....................................................1
Changes to Functional Block Diagram ..........................................1
Changes to Specifications ................................................................3
Changes to Absolute Maximum Ratings........................................5
Changes to Pin Function Descriptions ..........................................6
Changes to Figure 3 ..........................................................................8
Deleted Two TPCs ..........................................................................11
Changes to Figure 18 and Figure 19 .............................................11
Changes to BPDK Mode Section ..................................................21
Changes to Differential Refclk Enable Section ...........................24
Changes to Master Reset Section ..................................................24
Changes to Parallel I/O Operation Section .................................24
Changes to General Operation of the Serial
Interface Section..............................................................................27
Changes to Figure 50 ......................................................................27
Changes to Figure 65 ......................................................................36
Rev. E | Page 3 of 52
AD9852
GENERAL DESCRIPTION
The AD9852 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with an internal
high speed, high performance D/A converter to form a digitally
programmable, agile synthesizer function. When referenced to
an accurate clock source, the AD9852 generates a highly stable
frequency-, phase-, and amplitude-programmable cosine output
that can be used as an agile LO in communications, radar, and
many other applications. The innovative high speed DDS core
of the AD9852 provides 48-bit frequency resolution (1 μHz
tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits
ensures excellent SFDR.
The circuit architecture of the AD9852 allows the generation of
output signals at frequencies up to 150 MHz, which can be
digitally tuned at a rate of up to 100 million new frequencies
per second. The (externally filtered) cosine wave output can be
converted to a square wave by the internal comparator for agile
clock generator applications. The device provides two 14-bit
phase registers and a single pin for BPSK operation.
For higher-order PSK operation, the I/O interface can be used
for phase changes. The 12-bit cosine DAC, coupled with the
innovative DDS architecture, provides excellent wideband and
narrow-band output SFDR. When configured with the
comparator, the 12-bit control DAC facilitates static duty cycle
control in the high speed clock generator applications.
The 12-bit digital multiplier permits programmable amplitude
modulation, on/off output shaped keying, and precise amplitude
control of the cosine DAC output. Chirp functionality is also
included for wide bandwidth frequency sweeping applications.
The AD9852 programmable 4× to 20× REFCLK multiplier cir-
cuit internally generates the 300 MHz system clock from a lower
frequency external reference clock. This saves the user the expense
and difficulty of implementing a 300 MHz system clock source.
Direct 300 MHz clocking is also accommodated with either single-
ended or differential inputs. Single-pin, conventional FSK and the
enhanced spectral qualities of ramped FSK are supported. The
AD9852 uses advanced 0.35 μ CMOS technology to provide this
high level of functionality on a single 3.3 V supply.
The AD9852 is pin-for-pin compatible with the
AD9854
single-
tone synthesizer. The AD9852 is specified to operate over the
extended industrial temperature range of −40°C to +85°C.
OVERVIEW
The AD9852 digital synthesizer is a highly flexible device that
addresses a wide range of applications. The device consists of
an NCO with a 48-bit phase accumulator, a programmable
reference clock multiplier, an inverse sinc filter, a digital
multiplier, two 12-bit/300 MHz DACs, a high speed analog
comparator, and an interface logic. This highly integrated
device can be configured to serve as a synthesized LO agile
clock generator and FSK/BPSK modulator. The theory of
operation for the functional blocks of the device and a technical
description of the signal flow through a DDS device is provided
by Analog Devices, Inc., in the tutorial
A Technical Tutorial on
Digital Signal Synthesis.
The tutorial also provides basic
applications information for a variety of digital synthesis
implementations.
Rev. E | Page 4 of 52
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