HD74HC192RP datasheet, PDF - EEWORLD Datasheet

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HD74HC192RP: DescriptionDecade Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16, FP-16DN; Categorylogic logic; File Size73KB，13 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD74HC192RP Overview

Decade Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16, FP-16DN

HD74HC192RP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Hitachi （Renesas ）
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	unknown
Other features	TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
Counting direction	BIDIRECTIONAL
series	HC/UH
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	9.9 mm
Load capacitance (CL)	50 pF
Load/preset input	YES
Logic integrated circuit type	DECADE COUNTER
Maximum Frequency@Nom-Sup	19000000 Hz
MaximumI(ol)	0.004 A
Operating mode	SYNCHRONOUS
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	2/6 V
propagation delay (tpd)	345 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	3.9 mm

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HD74HC192/HD74HC193

Synchronous Up/Down Decade Counter (Dual Clock Line)

Synchronous Up/Donw 4-bit Binary Counter (Dual Clock Line)

Description

The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two

separate clock inputs, an up count input and a down count input. All outputs of the flip-flops are

simultaneously triggered on the low to high transition of either clock while the other input is held high.

The direction of counting is determined by which input is clocked.

These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs.

When the load input is taken low the data is loaded independently of either clock input. This feature allows

the counters to be used as divide-by-n counters by modifying the count length with the preset inputs.

In addition both counters can also be cleared. This is accomplished by inputting a high on the clear input.

All 4 internal stages are set to a low level independently of either count input.

Both a borrow and carry output are provided to enable cascading of both up and down counting functions.

The borrow output produces a negative going pulse when the counter underflows and the carry outputs a

pulse when the counter overflows. The counters can be cascaded by connecting the carry and borrow

outputs of one device to the count up and count down inputs, respectively, of the next device.

Features

•

High Speed Operation: t

(Clock Up or Count Down to Q) = 21 ns typ (C

= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V

= 2 to 6 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I

(static) = 4 µA max (Ta = 25°C)

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