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HD74HC137
3-to-8-line Decoder/Demultiplexer with Address Latch
REJ03D0569-0200
(Previous ADE-205-443)
Rev.2.00
Oct 11, 2005
Description
The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When
GL
goes
from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as
GL
remains
high no address changes will be recognized. Output enable controls, G
1
and
G
2
, control the state of the outputs
independently of the select or latch-enable inputs.
All of the outputs are high unless G
1
is high and
G
2
is low. The HD74HC137 is ideally suited for the implementation of
glitchfree decoders in stored-address applications in bus oriented systems.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
(A, B, C to Y) = 16.5 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 V to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
Ordering Information
Part Name
HD74HC137P
HD74HC137FPEL
HD74HC137RPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
PRSP0016DG-A
(FP-16DNV)
Package
Abbreviation
P
FP
RP
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Rev.2.00, Oct 11, 2005 page 1 of 9
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