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MC10H124
Quad TTL-to-MECL
Translator With TTL Strobe
Input
Description
The MC10H124 is a quad translator for interfacing data and control
signals between a saturated logic section and the MECL section of
digital systems. The 10H part is a functional/pinout duplication of the
standard MECL 10K™ family part, with 100% improvement in
propagation delay, and no increase in power−supply current.
Features
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MARKING DIAGRAMS*
16
MC10H124L
AWLYYWW
CDIP−16
L SUFFIX
CASE 620A
16
16
1
PDIP−16
P SUFFIX
CASE 648
1
MC10H124P
AWLYYWWG
1
•
Propagation Delay, 1.5 ns Typical
•
Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
•
Voltage Compensated
•
MECL 10K Compatible
•
Pb−Free Packages are Available*
5
6
7
4
2
3
1
12
15
11
GND = PIN 16
V
CC
( +5.0 VDC) = PIN 9
V
EE
( -5.2 VDC) = PIN 8
13
14
10
10H124
ALYWG
SOEIAJ−16
CASE 966
1 20
Figure 1. Logic Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
20 1
PLLC−20
FN SUFFIX
CASE 775
10H124G
AWLYYWW
QFN−16
MN SUFFIX
CASE 485G
A
WL, L
YY, Y
WW, W
G or
G
MC100
H124MN
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
June, 2010
−
Rev. 11
1
Publication Order Number:
MC10H124/D
MC10H124
GND C
OUT
D
OUT
D
OUT
Exposed Pad (EP)
B
OUT
A
OUT
B
OUT
A
OUT
A
IN
COMMON
STROBE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
C
OUT
D
OUT
D
OUT
C
OUT
D
IN
C
IN
V
CC
B
OUT
A
OUT
B
OUT
A
OUT
1
2
16
15
14
13
12
11
C
OUT
D
IN
C
IN
V
CC
MC10H124
3
4
5
6
7
8
10
9
B
IN
V
EE
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see Table 1.
A
IN
COMMON B
IN
V
EE
STROBE
Pin assignment for QFN16 Package.
Figure 2. Pin Assignment
Table 1. DIP CONVERSION TABLE
16−Pin DIL to 20−Pin PLCC
16 PIN DIL
20 PIN PLCC
1
2
2
3
3
4
4
5
5
7
6
8
7
9
8
10
9
12
10
13
11
14
12
15
13
17
14
18
15
19
16
20
Table 2. MAXIMUM RATINGS
Symbol
V
EE
V
CC
V
I
I
out
T
A
T
stg
Power Supply (V
CC
= 5.0 V)
Power Supply (V
EE
=
−5.2
V)
Input Voltage (V
CC
= 5.0 V) TTL
Output Current
−
Continuous
−
Surge
Operating Temperature Range
Storage Temperature Range
−
Plastic
−
Ceramic
Characteristic
Rating
−8.0
to 0
0 to +7.0
0 to V
CC
50
100
0 to +75
−55
to +150
−55
to +165
Unit
Vdc
Vdc
Vdc
mA
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC10H124
Table 3. ELECTRICAL CHARACTERISTICS
(V
EE
=
−5.2
V
±5%,
V
CC
= 5.0 V
±
5.0%)
0°
Symbol
I
E
I
CCH
I
CCL
I
R
Characteristic
Negative Power
Supply Drain Current
Positive Power
Supply Drain Current
Reverse Current
Pin 6
Pin 7
Forward Current
Pin 6
Pin 7
Input Breakdown Voltage
Input Clamp Voltage
High Output Voltage
Low Output Voltage
High Input Voltage
Min
−
−
−
−
−
−
−
5.5
−
−1.02
−1.95
2.0
Max
72
16
25
200
50
−12.8
−3.2
−
−1.5
−0.84
−1.63
−
Min
−
−
−
−
−
−
−
5.5
−
−0.98
−1.95
2.0
25°
Max
66
16
25
200
50
−12.8
−3.2
−
−1.5
−0.81
−1.63
−
Min
−
−
−
−
−
−
−
5.5
−
−0.92
−1.95
2.0
75°
Max
72
18
25
200
50
mA
−12.8
−3.2
−
−1.5
−0.735
−1.60
−
Vdc
Vdc
Vdc
Vdc
Vdc
Unit
mA
mA
mA
I
F
V
(BR)in
V
I
V
OH
V
OL
V
IH
V
IL
Low Input Voltage
−
0.8
−
0.8
−
0.8
Vdc
1. Each MECL 10H™ series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.
Outputs are terminated through a 50
W
resistor to
−2.0
V.
Table 4. AC CHARACTERISTICS
0°
Symbol
t
pd
t
r
t
f
25°
Max
2.5
1.5
1.5
Min
0.55
0.5
0.5
Max
2.65
1.6
1.6
Min
0.85
0.5
0.5
75°
Max
3.1
1.7
1.7
Unit
ns
ns
ns
Characteristic
Propagation Delay
Rise Time
Fall Time
Min
0.55
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10H124
APPLICATIONS INFORMATION
The MC10H124 has TTL−compatible inputs and MECL
complementary open−emitter outputs that allow use as an
inverting/non−inverting translator or as a differential line
driver. When the common strobe input is at the low−logic
level, it forces all true outputs to a MECL low−logic state
and all inverting outputs to a MECL high−logic state.
ORDERING INFORMATION
Device
MC10H124FN
MC10H124FNG
MC10H124FNR2
MC10H124FNR2G
MC10H124L
MC10H124M
MC10H124MG
MC10H124MEL
MC10H124MELG
MC10H124P
MC10H124PG
MC10H125MNG
MC10H124MNTXG
Package
PLCC−20
PLCC−20
(Pb−Free)
PLCC−20
PLCC−20
(Pb−Free)
CDIP−16
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
PDIP−16
PDIP−16
(Pb−Free)
QFN−16, 3 x 3 mm
(Pb−Free)
QFN−16, 3 x 3 mm
(Pb−Free)
Shipping
†
46 Units / Rail
46 Units / Rail
500 / Tape & Reel
500 / Tape & Reel
25 Units / Rail
50 Units / Rail
50 Units / Rail
2000 / Tape & Reel
2000 / Tape & Reel
25 Units / Rail
25 Units / Rail
123 Units / Rail
3000 / Tape & Reel
An advantage of this device is that TTL−level information
can be transmitted differentially, via balanced twisted pair
lines, to MECL equipment, where the signal can be received
by the MC10H115 or MC10H116 differential line receivers.
The power supply requirements are ground, +5.0 V, and
−5.2
V.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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4
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