LH7A400
Data Sheet
FEATURES
• 32-bit ARM9TDMI™ RISC Core
– 16KB Cache: 8KB Instruction and 8KB Data
– MMU (Windows CE™ Enabled)
– Up to 250 MHz; see Table 1 for options
• 80KB On-Chip Static RAM
• Programmable Interrupt Controller
• External Bus Interface
– Up to 125 MHz; see Table 1 for options
– Asynchronous SRAM/ROM/Flash
– Synchronous DRAM/Flash
– PCMCIA
– CompactFlash
• Clock and Power Management
– 32.768 kHz and 14.7456 MHz Oscillators
– Programmable PLL
• Programmable LCD Controller
– Up to 1,024 × 768 Resolution
– Supports STN, Color STN, AD-TFT, HR-TFT, TFT
– Up to 64 k-Colors and 15 Gray Shades
• DMA (10 Channels)
– AC97
– MMC
– USB
• USB Device Interface (USB 2.0, Full Speed)
• Synchronous Serial Port (SSP)
– Motorola SPI™
– Texas Instruments SSI
– National MICROWIRE™
• Three Programmable Timers
• Three UARTs
– Classic IrDA (115 kbit/s)
•
•
•
•
•
•
•
•
•
•
32-Bit System-on-Chip
Smart Card Interface (ISO7816)
Two DC-to-DC Converters
MultiMediaCard™ Interface
AC97 Codec Interface
Smart Battery Monitor Interface
Real Time Clock (RTC)
Up to 60 General Purpose I/Os
Watchdog Timer
JTAG Debug Interface and Boundary Scan
Operating Voltage
– 1.8 V Core
– 3.3 V Input/Output
• 5 V Tolerant Digital Inputs (except oscillator pins)
– Oscillator pins P15, P16, R13, and T13 are
1.8 V ± 10%.
• Operating Temperature
– 0°C to +70°C Commercial
– -40°C to +85°C Industrial (With Clock Frequency
Reduction)
• 256-Ball PBGA or 256-Ball CABGA Package
DESCRIPTION
The LH7A400, powered by an ARM922T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
This high degree of integration lowers overall
system costs, reduces development cycle time and
accelerates product introduction.
NOTE:
Devices containing lead-free solder formulations have differ-
ent reflow temperatures than leaded-solder formulations.
When using both solder formulations on the same PC board,
designers should consider the effect of different reflow tem-
peratures on the overall PCB assembly process.
Table 1. LH7A400 Versions
PART NUMBER
1
LH7A400N0F076xx
2
LH7A400N0G076xx
2
LH7A400N0B000xx
LH7A400N0E000xx
LH7A400N0F000xx
2
LH7A400N0G000xx
2
CORE CLOCK BUS CLOCK
250 MHz
245 MHz
200 MHz
100 MHz
195 MHz
Motorola SPI is a trademark of Motorola, Inc.
National Semiconductor MICROWIRE is a trademark of
National Semiconductor Corporation.
Windows CE is a trademark of Microsoft Corporation.
LOW POWER CURRENT BY MODE (TYP.)
Run = 250 mA; Halt = 50 mA; Standby = 129
μA
TEMP. RANGE
0°C to +70°C
125 MHz
-40°C to +85°C
0°C to +70°C
Run = 125 mA; Halt: 25 mA; Standby = 42
μA
-40°C to +85°C
NOTES:
1. Where ‘xx’ is a two digit revision number, e.g. B2; refer to
www.sharpmcu.com for a list of all the active revisions
2. Lead-free part
Data Sheet
Version 1.2
1
LH7A400
32-Bit System-on-Chip
Table 2. Functional Pin List (Cont’d)
PBGA
PIN
H6
D4
E4
C2
R13
T13
P16
P15
P14
J6
K11
K10
P13
M12
L12
M15
N13
L16
L15
L14
H11
K12
J15
J13
J10
H15
H13
G15
G11
G12
F15
F12
E14
D16
H10
D14
F10
A16
A14
B13
C13
E12
G10
B12
B11
D11
CABGA
PIN
D1
E2
F2
D2
R14
R15
N14
M13
M12
J5
P14
P16
N15
N16
L11
L13
L14
K11
L16
K14
J15
J12
J10
H16
H14
H11
G16
G9
G14
G12
F15
E15
D16
F12
E13
D14
E12
B16
D12
A16
B13
B14
C12
A14
B12
A12
SIGNAL
nURESET
WAKEUP
nPWRFL
nEXTPWR
XTALIN
XTALOUT
XTAL32IN
XTAL32OUT
CLKEN
PGMCLK
nCS0
nCS1
nCS2
nCS3/
nMMSPICS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
Data Bus
LOW
LOW
12 mA
I/O
DESCRIPTION
User Reset; should be pulled HIGH for normal or
JTAG operation.
Wake Up
Power Fail Signal
External Power
14.7456 MHz Crystal Oscillator pins. An external
clock source can be connected to XTALIN leaving
XTALOUT open.
32.768 kHz Real Time Clock Crystal Oscillator
pins. An external clock source can be connected to
XTAL32IN leaving XTAL32OUT open.
External Osc Clock Enable Output
Programmable Clock (14.7456 MHz MAX.)
Asynch Memory Chip Select 0
Asynch Memory Chip Select 1
Asynch Memory Chip Select 2
• Asynch Memory Chip Select 3
• MultiMediaCard SPI Mode Chip Select
RESET
STATE
Input
(Schmitt)
Input
(Schmitt)
Input
(Schmitt)
Input
(Schmitt)
Input
LOW
Input
Output
LOW
LOW
HIGH
HIGH
HIGH
HIGH:
nCS3
STANDBY
STATE
Input
Input
Input
Input
Input
LOW
Input
Output
LOW
LOW
HIGH
HIGH
HIGH
HIGH
8 mA
8 mA
12 mA
12 mA
12 mA
12 mA
OUTPUT
I/O NOTES
DRIVE
I
I
I
I
I
O
I
O
I/O
O
I/O
I/O
I/O
I/O
3
3
3
3
4
Version 1.2
Data Sheet
32-Bit System-on-Chip
LH7A400
Table 2. Functional Pin List (Cont’d)
PBGA
PIN
M16
N14
M13
K16
K15
K14
J8
J16
J14
J9
H16
H14
G16
G14
G13
F16
F14
E16
E13
F11
D15
C16
B16
A15
A13
G8
F8
A8
D8
C8
D10
B10
C10
G9
A10
C14
D13
E11
A12
C12
C11
F9
A9
B9
CABGA
PIN
M15
M16
L15
K12
K13
K16
J13
J11
J16
H15
H10
H12
G15
G10
G11
F16
E16
F13
E14
D15
C16
C15
C14
B15
E11
D8
B7
A7
C8
F8
D9
E9
A10
A11
B10
C13
A15
D11
E10
A13
B11
C11
C9
A9
SIGNAL
A0/nWE1
A1/nWE2
A2/SA0
A3/SA1
A4/SA2
A5/SA3
A6/SA4
A7/SA5
A8/SA6
A9/SA7
A10/SA8
A11/SA9
A12/SA10
A13/SA11
A14/SA12
A15/SA13
A16/SB0
A17/SB1
A18
A19
A20
A21
A22
A23
A24
A25/SCIO
A26/SCCLK
A27/SCRST
nOE
nWE0
nWE3
CS6/SCKE1_2
CS7/SCKE0
SCKE3
SCLK
nSCS0
nSCS1
nSCS2
nSCS3
nSWE
nCAS
nRAS
DQM0
DQM1
• Asynch Memory Address Bus
• Smart Card Interface I/O (Data)
• Asynch Memory Address Bus
• Smart Card Interface Clock
• Asynch Memory Address Bus
• Smart Card Interface Reset
Asynch Memory Output Enable
Asynch Memory Write Byte Enable 0
Asynch Memory Write Byte Enable 3
• Asynch Memory Chip Select 6
• Synch Memory Clock Enable 1 or 2
• Asynch Memory Chip Select 7
• Synch Memory Clock Enable 0
Synch Memory Clock Enable 3
Synch Memory Clock
Synch Memory Chip Select 0
Synch Memory Chip Select 1
Synch Memory Chip Select 2
Synch Memory Chip Select 3
Synch Memory Write Enable
Synch Memory Column Address Strobe Signal
Synch Memory Row Address Strobe Signal
Synch Memory Data Mask 0
Synch Memory Data Mask 1
LOW: A25
LOW: A26
LOW: A27
HIGH
HIGH
HIGH
LOW: CS6
LOW: CS7
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
12 mA
12 mA
12 mA
12 mA
12 mA
8 mA
12 mA
12 mA
12 mA
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
2
Asynchronous Address Bus
LOW
LOW
12 mA
I/O
• Asynch Address Bus
• Synch Device Bank Address 0
• Asynch Address Bus
• Synch Device Bank Address 1
LOW
LOW
LOW
LOW
12 mA
12 mA
I/O
I/O
• Asynchronous Address Bus
• Synchronous Address Bus
LOW
LOW
12 mA
I/O
DESCRIPTION
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 1
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 2
RESET
STATE
HIGH:
nWE1
HIGH:
nWE2
STANDBY
STATE
HIGH
HIGH
OUTPUT
I/O NOTES
DRIVE
12 mA
12 mA
I/O
I/O
See Note
I/O
2
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data Sheet
Version 1.2
5