Integrated
Circuit
Systems, Inc.
ICS873033
H
IGH
S
PEED
, ÷4 D
IFFERENTIAL
-
TO
-
3.3V, 5V LVPECL/ECL C
LOCK
G
ENERATOR
F
EATURES
•
One
differential 3.3V, 5V LVPECL / ECL output
•
One
differential PCLK, nPCLK input pair
•
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Input frequency: 3.2GHz (maximum)
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Additive phase jitter, RMS: 0.20ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 3.0V to 5.5V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -5.5V to -3.0V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS873033 is a high speed, high perfor-
mance Differential-to-3.3V, 5V LVPECL/ECL
HiPerClockS™
Clock Generator a n d a m e m b e r o f t h e
HiPerClockS ™ family of High Perfor mance
Clock Solutions from ICS. The ICS873033
is characterized to operate from either a 3.3V or a 5V
power supply.
IC
S
B
LOCK
D
IAGRAM
RESET
P
IN
A
SSIGNMENT
RESET
PCLK
nPCLK
V
BB
1
2
3
4
8
7
6
5
Vcc
Q
nQ
V
EE
PCLK
nPCLK
V
BB
÷4
Q
nQ
ICS873033
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
ICS873033
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
873033AM
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 19, 2005
1
Integrated
Circuit
Systems, Inc.
ICS873033
H
IGH
S
PEED
, ÷4 D
IFFERENTIAL
-
TO
-
3.3V, 5V LVPECL/ECL C
LOCK
G
ENERATOR
Type
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6, 7
8
Name
RESET
PCLK
nPCLK
V
BB
V
EE
nQ, Q
V
CC
Input
Input
Input
Output
Power
Output
Power
Pulldown Reset pin. Single-ended 100h LVPECL interface levels.
Pulldown Clock input. Default LOW when left floating. LVPECL interface levels.
Pulldown Clock input. LVPECL interface levels.
Bias voltage.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
Parameter
Input Pulldown Resistor
Test Conditions
Minimum
Typical
75
Maximum
Units
kΩ
T
ABLE
3. T
RUTH
T
ABLE
Inputs
PCLK
X
nPCLK
X
RESET
LH
Q
L
÷4
Outputs
nQ
H
÷4
LH
HL
L
LH = LOW to HIGH transistion
HL = HIGH to LOW transistion
PCLK
t
RR
RESET
t
PW
Q
F
IGURE
1. T
IMING
D
IAGRAM
873033AM
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 19, 2005
Integrated
Circuit
Systems, Inc.
ICS873033
H
IGH
S
PEED
, ÷4 D
IFFERENTIAL
-
TO
-
3.3V, 5V LVPECL/ECL C
LOCK
G
ENERATOR
6V (LVPECL mode, V
EE
= 0)
-6V (ECL mode, V
CC
= 0)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
- 0.5V
50mA
100mA
± 0.5mA
-65°C to 150°C
112.7°C/W (0 lfpm)
101.7°C/W (0 m/s)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
Package Thermal Impedance,
θ
JA
Operating Temperature Range, TA -40°C to +85°C
(Junction-to-Ambient) for 8 Lead SOIC
(Junction-to-Ambient) for 8 Lead TSSOP
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.0V
TO
5.5V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
5.5
30
Units
V
mA
T
ABLE
4B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference
Min
2.175
1.405
2.075
1.43
1.86
-40°C
Typ
2.275
1.545
Max
2.38
1.68
2.36
1.765
1.98
Min
2.225
1.425
2.075
1.43
1.86
25°C
Typ
2.295
1.52
Max
2.37
1.615
2.36
1.765
1.98
Min
2.295
1.44
2.075
1.43
1.86
85°C
Typ
2.33
1.535
Max
2.365
1.63
2.36
1.765
1.98
Units
V
V
V
V
V
150
800
1200
150
800
1200
150
Peak-to-Peak Input Voltage
Input High Voltage
1.2
3.3
1.2
3.3
1.2
V
CMR
Common Mode Range; NOTE 2, 3
Input
150
150
I
IH
PCLK, nPCLK
High Current
Input
-10
-10
I
IL
-10
PCLK, nPCLK
Low Current
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3V to -2.2V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
800
1200
3.3
150
m
V
V
µA
µA
873033AM
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 19, 2005
Integrated
Circuit
Systems, Inc.
ICS873033
H
IGH
S
PEED
, ÷4 D
IFFERENTIAL
-
TO
-
3.3V, 5V LVPECL/ECL C
LOCK
G
ENERATOR
-40°C
Typ
3.975
3.245
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference
Min
3.875
3.105
3.775
3.13
3.56
Max
4.08
3.38
4.06
3.465
3.68
Min
3.925
3.125
3.775
3.13
3.56
25°C
Typ
3.995
3.22
Max
4.07
3.315
4.06
3.465
3.68
Min
3.995
3.14
3.775
3.13
3.56
85°C
Typ
4.03
3.235
Max
4.065
3.33
4.06
3.465
3.68
Units
V
V
V
V
V
150
800
1200
150
800
1200
150
Peak-to-Peak Input Voltage
Input High Voltage
1.2
5
1.2
5
1.2
V
CMR
Common Mode Range; NOTE 2, 3
Input
150
150
I
IH
PCLK, nPCLK
High Current
Input
-10
-10
I
IL
-10
PCLK, nPCLK
Low Current
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +2V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
800
1200
5
150
m
V
V
µA
µA
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-3.0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference
-40°C
Min
-1.125
-1.895
-1.225
-1.87
-1.44
25°C
Max
-0.92
-1.62
-0.94
-1.535
-1.32
85°C
Max
-0.93
-1.685
-0.94
-1.535
-1.32
Typ
-1.025
-1.755
Min
-1.075
-1.875
-1.225
-1.87
-1.44
Typ
-1.005
-1.78
Min
-1.005
-1.86
-1.225
-1.87
-1.44
Typ
-0.97
-1.765
Max
-0.935
-1.67
-0.94
-1.535
-1.32
Units
V
V
V
V
V
150
800
1200
150
800
1200
150
Peak-to-Peak Input Voltage
Input High Voltage
V
EE
+1.2V
0
V
EE
+1.2V
0
V
EE
+1.2V
V
CMR
Common Mode Range; NOTE 2, 3
Input
150
150
PCLK, nPCLK
I
IH
High Current
Input
-10
-10
-10
PCLK, nPCLK
I
IL
Low Current
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
800
1200
0
150
m
V
V
µA
µA
873033AM
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 19, 2005
Integrated
Circuit
Systems, Inc.
ICS873033
H
IGH
S
PEED
, ÷4 D
IFFERENTIAL
-
TO
-
3.3V, 5V LVPECL/ECL C
LOCK
G
ENERATOR
OR
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-3.0V
Symbol
f
MAX
t
PD
t
jit(Ø)
t
RR
t
R
/t
F
Parameter
Input Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
155.52MHz, Integration Range
12kHz - 20MHz; Refer to Additive
Phase Jitter Section
Set/Reset Recovery; NOTE 2
Output Rise/Fall Time
20% to 80%
300
Min
V
CC
= 3.0V
TO
5.5V; V
EE
= 0V
-40°C
Typ
Ma x
3.2
475
0.20
150
100
100
250
200
10 0
300
Min
25°C
Typ
430
0.20
100
250
200
100
Max
3.2
530
350
Min
85°C
Typ
450
0.20
100
250
480
Max
3.2
550
Units
GH z
ps
ps
ps
ps
ps
t
PW
Pulse Width; NOTE 3 RESET
550
480
55 0
480
550
All parameters are measured at f
≤
1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: See Figure 1, Timing Diagram.
873033AM
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 19, 2005
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