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NAND256W4A0DN1

Description
16MX16 FLASH 3V PROM, 12000ns, PDSO48, 12 X 20 MM, TSOP-48
Categorystorage    storage   
File Size150KB,5 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

NAND256W4A0DN1 Overview

16MX16 FLASH 3V PROM, 12000ns, PDSO48, 12 X 20 MM, TSOP-48

NAND256W4A0DN1 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSTMicroelectronics
Parts packaging codeTSOP
package instructionTSOP1,
Contacts48
Reach Compliance Codecompliant
ECCN code3A991.B.1.A
Maximum access time12000 ns
JESD-30 codeR-PDSO-G48
JESD-609 codee0
length18.4 mm
memory density268435456 bit
Memory IC TypeFLASH
memory width16
Number of functions1
Number of terminals48
word count16777216 words
character code16000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX16
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programming voltage3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width12 mm
NAND FLASH
528 Byte, 264 Word Page Family
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
1.8V, 3V Supply Flash Memories
DATA BRIEFING
FEATURES SUMMARY
s
HIGH DENSITY NAND FLASH MEMORIES
– Up to 1 Gbit memory array
– Up to 32Mbit spare area
– Cost effective solutions for mass storage ap-
plications
s
Figure 1. Packages
NAND INTERFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
TSOP48
12 x 20 mm
s
SUPPLY VOLTAGE
– 1.8V device: V
CC
= 1.65 to 1.95V
– 3.0V device: V
CC
= 2.7 to 3.6V
FBGA
s
PAGE SIZE
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
VFBGA63 8.5x15x1 mm
TFBGA63 8.5x15x1.2 mm
VFBGA63 9x11x1 mm
s
BLOCK SIZE
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
s
AUTOMATIC PAGE 0 READ AT POWER-UP
OPTION
– Boot from NAND support
– Automatic Memory Download
s
PAGE READ / PROGRAM
– Random access: 12µs (max)
– Sequential access: 50ns (min)
– Page program time: 200µs (typ)
s
s
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
– Program/Erase locked during Power transi-
tions
s
COPY BACK PROGRAM MODE
– Fast page copy without external buffering
CACHE PROGRAM MODE
– Internal Cache Register to improve the pro-
gram throughput
s
s
DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
s
FAST BLOCK ERASE
– Block erase time: 2ms (Typ)
STATUS REGISTER
ELECTRONIC SIGNATURE
CHIP ENABLE ‘DON’T CARE’ OPTION
– Simple interface with microcontroller
s
DEVELOPMENT TOOLS
– Error Correction Code software and hard-
ware models
– Bad Blocks Management and Wear Leveling
algorithms
– PC Demo board with simulation software
– File System OS Native reference software
– Hardware simulation models
s
s
s
August 2003
For further information please contact the STMicroelectronics distributor nearest to you.
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