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MT5C1008SJ-25LXT

Description
Standard SRAM, 128KX8, 25ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32
Categorystorage    storage   
File Size146KB,13 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT5C1008SJ-25LXT Overview

Standard SRAM, 128KX8, 25ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32

MT5C1008SJ-25LXT Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeSOJ
package instruction0.300 INCH, PLASTIC, SOJ-32
Contacts32
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time25 ns
Other featuresTTL-COMPATIBLE INPUTS & OUTPUTS
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
JESD-609 codee0
length20.98 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height3.68 mm
Maximum standby current0.001 A
Minimum standby current2 V
Maximum slew rate0.135 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.67 mm
OBSOLETE
MT5C1008
128K x 8 SRAM
SRAM
FEATURES
• High speed: 12, 15, 20 and 25
• Available in 300 mil- and 400 mil-wide SOJ packages
• High-performance, low-power, CMOS double-metal
process
• Single +5V
±10%
power supply
• Easy memory expansion with
/
C
?
E1, CE2 and
?
OE
/
options
• All inputs and outputs are TTL-compatible
• Fast
/
O
/
E access time: 6ns
128K x 8 SRAM
WITH OUTPUT ENABLE
PIN ASSIGNMENT (Top View)
32-Pin DIP
(SA-6)
NC
A16
A14
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ8
DQ7
DQ6
DQ5
DQ4
32-Pin SOJ
(SD-4, SD-5)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ8
DQ7
DQ6
DQ5
DQ4
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
• Packages
Plastic DIP (400 mil)
Plastic SOJ (400 mil)
Plastic SOJ (300 mil)
MARKING
-12
-15
-20
-25
None
DJ
SJ
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
• 2V data retention (optional)
L
• 2V data retention, low power (optional) LP
• Temperature
Commercial (0°C to +70°C)
Industrial
(-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended
(-55°C to +125°C)
None
IT
AT
XT
• Part Number Example: MT5C1008DJ-20 L
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5C1008 is organized as a 131,072 x 8 SRAM using
a four-transistor memory cell with a high-speed, low-power
CMOS process. Micron SRAMs are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers dual chip enables (/C
?
E1, CE2) and an output
enable (?O
/
E). This enhancement can place the outputs in
High-Z for additional flexibility in system design.
MT5C1008
S17.pm5 – Rev. 1/95
Writing to these devices is accomplished when write
enable (?W
/
E) and C
?
E1 inputs are both LOW and CE2 is
/
HIGH. Reading is accomplished when
?
W
/
E and CE2 remain
HIGH and
/
C
?
E1 and O
/
E go LOW. The device offers reduced
?
power standby modes when disabled. This allows system
designers to meet low standby power requirements.
The “L” and “LP” versions each provide a 70% reduction
in CMOS standby current (I
SB
2
) over the standard version.
The “LP” version also provides a 90% reduction in TTL
standby current (I
SB
1
). This is achieved by including gated
inputs on the
?
W
/
E,
?
O
/
E and address lines. The gated inputs
also facilitate the design of battery backed systems where
the designer needs to protect against inadvertent battery
current drain during power-down, when inputs may be at
undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL-compatible.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.

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